Smart Sampling for Block Family Scan in Memory Sub-systems
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Solution Overview
Problem
The existing memory sub-systems face challenges in maintaining accurate voltage bin assignments for block families due to temporal voltage shift, leading to increased bit error rates and resource inefficiency, as frequent calibration scans are necessary to mitigate these issues but consume significant resources and can cause performance latency.
Innovation Solution
The memory sub-system employs adaptive calibration scan frequency techniques based on changing characteristics such as power state, workload, and block family age, prioritizing scans for younger bins and reducing frequency during low demand periods to maintain accurate voltage bin assignments with minimal resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If frequent calibration scans are performed to maintain accurate voltage bin assignments, then read level calibration accuracy is improved, but resource consumption and performance latency increase
Solution Approach 1:
The patent implements dynamic calibration scan frequency adjustment based on block family age and temporal voltage shift characteristics. Younger block families undergo more frequent calibration scans, while older block families are scanned less frequently. This dynamic approach maintains voltage bin assignment accuracy for critical young blocks while reducing overall scan frequency to improve system performance and reduce latency.
Solution Approach 2:
The patent applies different calibration scan frequencies to different block families based on their specific characteristics (age, voltage shift patterns). Instead of uniform scanning, each block family receives customized scan frequency tailored to its temporal voltage shift behavior, optimizing the balance between calibration accuracy and system performance.
2Measurement precision
If calibration scans are performed at high frequency, then voltage bin assignment accuracy is maintained, but resource consumption increases
Solution Approach 1:
The system dynamically adjusts calibration scan frequency based on block family age and observed temporal voltage shift characteristics. High-frequency scans are applied only to younger block families that exhibit greater voltage drift, while older block families receive reduced scan frequency, thereby maintaining calibration accuracy where needed while conserving system resources.
Solution Approach 2:
The patent changes the calibration scan frequency parameter based on block family characteristics. By monitoring temporal voltage shift and block age, the system adjusts the scan frequency parameter dynamically, applying higher frequencies to blocks requiring precise calibration and lower frequencies to blocks with stable voltage characteristics, thus optimizing resource consumption.
Data Source
AI summary
A system can include a memory device and a processing device to perform operations that include performing a block family calibration scan of the memory device, wherein the calibration scan comprises a plurality of scan iterations, wherein each scan iteration is initiated in accordance with at least one threshold scan criterion, and wherein each scan iteration comprises identifying at least one first voltage bin, wherein each first voltage bin is associated with a plurality of read level offsets, identifying, according to a block family creation order, an oldest block family from a plurality of block families associated with the first voltage bin, and updating at least one bin pointer of the oldest block family based on a data state metric of at least one block of the oldest block family.