Sense Amplifier Data Latch Structure for Non-Volatile Memory
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Solution Overview
Problem
Current non-volatile memory technologies face challenges in achieving high capacity and performance due to noise and interference among closely packed memory cells, which limit sensing accuracy and storage capacity.
Innovation Solution
The implementation of an efficient data latch structure and sense amplifier circuit that uses a combination of dynamic and static data latches to manage bit line voltages, allowing for three different programming levels and reducing noise through state-dependent lockout techniques to enhance programming speed and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are closely packed to increase storage capacity, then memory density increases, but noise and interference increase which limits sensing accuracy
Solution Approach 1:
The patent segments the memory array into multiple blocks and implements block-level lockout mechanisms. When noise or interference is detected in a particular block, sensing operations can be locked out for that specific block while continuing in other blocks, thereby maintaining overall sensing accuracy despite high density packing.
Solution Approach 2:
The patent introduces reference cells and reference sensing operations as intermediaries to measure and compensate for noise and interference. By comparing data cell readings with reference cell readings, the system can identify and correct for noise effects, maintaining sensing accuracy in closely packed memory configurations.
2Measurement precision
If sense amplifier circuitry is added to improve sensing accuracy, then measurement precision improves, but device complexity increases
Solution Approach 1:
The patent merges the reference sensing circuitry with the data sensing circuitry within the same sense amplifier structure. By combining these functions into a unified circuit design, the patent achieves improved sensing accuracy through reference comparisons while avoiding the complexity overhead of completely separate reference and data sensing paths.
Solution Approach 2:
The sense amplifier circuitry is designed to perform multiple functions: it can sense both data cells and reference cells, and can operate in different modes (normal sensing, reference sensing, lockout). This multi-functionality allows a single circuit design to provide enhanced sensing accuracy without proportionally increasing device complexity.
3Measurement precision
If lockout techniques are implemented to reduce noise interference, then sensing accuracy improves, but programming speed decreases
Solution Approach 1:
The patent implements dynamic lockout mechanisms that adapt to actual noise conditions. Rather than applying static lockout to entire blocks, the system dynamically determines which specific cells or sub-blocks require lockout based on real-time noise measurements, allowing programming operations to continue at full speed in unaffected areas while maintaining sensing accuracy where needed.
Solution Approach 2:
The lockout technique is applied locally to specific memory cells or small groups of cells that exhibit noise problems, rather than applying blanket lockout to entire blocks. This localized approach maintains programming speed for the majority of cells while improving sensing accuracy only where interference is detected.
Data Source
AI summary
A non-volatile memory includes an data latch structure for programming bit lines using at least three programming levels. A sense amplifier includes a first data latch for controlling the voltage of a corresponding bit line, and a second static data latch with scan circuitry for performing logic operations on the program data and sense results. The sense amplifier scans low verify sense results with program data to generate reduced programming data. The reduced programming data is transferred out of the first data latch after sensing for all states and the program data is scanned to generate program enable/inhibit data which is stored in the first data latch. After setting the bit line to a program inhibit or program enable level, the reduced programming data is transferred back to the first data latch. The bit lines for reduced programming are then adjusted to the reduced programming level.