Boost Generation Circuit Leakage Reduction
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Solution Overview
Problem
Current memory circuit boost generation circuits face issues with boost drop and leakage, leading to reduced write yield due to inefficiencies in generating a negative boost voltage for write operations in memory devices.
Innovation Solution
The introduction of alternative circuit topologies for the boost generation circuit, which include changes in the configuration of capacitive elements and switches, such as direct coupling of the gate of PMOS transistor M4 to the Cap_Boost_G node and coupling the drain of transistor M3 to a power supply rail, reduces leakage and ensures effective generation of a more negative boost voltage without impacting area, power, or performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional boost generation circuit topology is used, then circuit area and power consumption are maintained, but leakage increases and boost voltage becomes less negative
Solution Approach 1:
The boost generation circuit is segmented into distinct functional blocks: a first capacitive element (C1) for voltage storage, a second capacitive element (C2) for boost generation, and multiple switches (S1-S4) for controlled connectivity. This segmentation allows independent optimization of each component to minimize leakage while maintaining boost voltage generation capability.
Solution Approach 2:
The patent extracts and eliminates leakage paths from the conventional circuit topology by removing direct connection paths that allow unwanted current flow. The switched capacitor configuration isolates capacitive elements from leakage-prone transistor channels when not actively charging or discharging, effectively taking out leakage paths from the functional circuit.
2Reliability
If conventional boost generation circuit topology is used, then circuit structure is simple, but boost voltage magnitude is insufficient
Solution Approach 1:
The first capacitive element C1 is pre-charged to a reference voltage level before the write operation begins. This preliminary charging action ensures that when the switched capacitor configuration activates, the boost voltage can be generated immediately with the required magnitude, rather than requiring time-consuming charging during the critical write window.
Solution Approach 2:
The patent changes the operational parameters of the capacitor network by dynamically switching between different capacitor configurations. During charge phase, C1 is connected to voltage rail; during boost phase, C1 and C2 are reconfigured to generate the negative boost voltage. This parameter change approach enables the circuit to achieve higher boost voltage magnitude while maintaining area efficiency.
3Reliability
If switched capacitor configuration is implemented, then leakage is reduced and boost voltage is improved, but circuit complexity increases
Solution Approach 1:
The switched capacitor network serves multiple functions within a single circuit structure: voltage storage (C1), voltage boosting (C1+C2), and leakage prevention (switched isolation). The same capacitive elements and switches that generate the negative boost voltage also function to isolate and prevent leakage paths, eliminating the need for separate leakage-blocking components and reducing overall circuit complexity despite the switched configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These alternative circuit topologies enhance the write yield by generating a more negative boost voltage, reducing leakage paths and improving the efficiency of the boost generation process, thereby increasing the voltage swing for write operations in memory circuits.
Implementation Method 1
a first capacitive element having a first terminal coupled to a first node of the boost generation circuit
Data Source
AI summary
Certain aspects of the present disclosure provide methods and apparatus for generating a negative boost voltage for memory write operations. One example memory circuit generally includes at least one memory bank, a write circuit coupled to the at least one memory bank, and a boost generation circuit coupled to the write circuit. The boost generation circuit generally includes a first node coupled to a reference potential node of the write circuit; a second node; a first capacitive element having a first terminal coupled to the first node of the boost generation circuit; a first switch configured to selectively couple the first node to a reference potential node for the memory circuit; and a second switch configured to selectively couple a second terminal of the first capacitive element to the second node of the boost generation circuit.