Semiconductor Memory Column Control Circuit for NAND Flash LM Flag Data
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Solution Overview
Problem
NAND type flash memory devices face inefficiencies in access speed and power consumption due to the need for interleave operations and multilevel storage systems, particularly in identifying and managing LM flag data across memory cores during read and write operations.
Innovation Solution
A semiconductor memory device configuration with column control circuits that perform LM address scans to determine the presence of LM flag data in memory cores, allowing for selective reading and omitting unnecessary operations, thereby reducing power consumption and enhancing performance by executing read operations only in cores with LM flag data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If read operations are performed in all memory cores during interleave operations, then data access completeness is ensured, but power consumption increases and access speed decreases due to unnecessary operations in cores without LM flag data
Solution Approach 1:
The patent applies partial action by performing read operations only in memory cores that contain LM flag data, rather than in all memory cores. The column control circuit identifies which cores have LM flag data and selectively executes read operations only in those cores, eliminating unnecessary operations in cores without LM flag data, thereby reducing power consumption and improving access speed
Solution Approach 2:
The patent applies preliminary action by performing an LM address scan operation before the actual read operation to identify which memory cores contain LM flag data. This preliminary identification allows the system to prepare a list of target cores and execute subsequent read operations only in those cores, avoiding unnecessary operations and optimizing both power consumption and access speed
2Reliability
If LM flag data is always read during read operations, then write operation progression status is always confirmed, but access speed decreases due to unnecessary read operations in cores without LM flag data
Solution Approach 1:
The patent applies partial action by reading LM flag data only from memory cores that are identified to contain such data through the LM address scan. Instead of universally reading LM flag data from all cores during every read operation, the system selectively performs this operation only where necessary, maintaining reliable write status tracking while improving access speed by eliminating redundant reads
Solution Approach 2:
The patent extracts the LM flag data reading operation from the universal read process and applies it only to specific memory cores that contain LM flag data. By separating this operation and applying it selectively based on LM address scan results, the system maintains necessary write operation monitoring while removing unnecessary delays from cores without LM flag data
Data Source
AI summary
At least one of a plurality of columns is an LM column for storing LM flag data indicating a progression state of a write operation. Each of column control circuits performs an LM address scan operation for confirming whether the LM column exists in a corresponding memory core or not. Each of the column control circuits stores a result of that LM address scan operation in a register. In various kinds of operations after the LM address scan operation, each of the column control circuits executes an operation of reading the LM flag data from the LM column in the corresponding one of the memory cores when data retained in the register is first data, and omits executing an operation of reading the LM flag data from the LM column in the corresponding one of the memory cores when data retained in the register is second data.