PRAM Block Write Algorithm Power Reduction
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Solution Overview
Problem
Phase Change Random Access Memory (PRAM) write operations consume high power due to voltage effects on unselected cells in dense cross-point array architectures, leading to inefficient energy usage.
Innovation Solution
Implementing a write algorithm that combines selective valid pages read and copy-back operations, where invalid pages are identified and erased bitline-wise, with valid data copied back row-by-row, reducing power consumption by up to 40% compared to prior art algorithms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high voltage drop is applied to switch a cell from high to low-resistance state, then the write operation is successful, but unselected cells on the same row or column suffer from voltage variations causing power consumption and write disturb
Solution Approach 1:
The patent segments the memory array into multiple sub-arrays, allowing write operations to be performed on smaller portions of the array at a time. This reduces the number of unselected cells exposed to voltage drops, thereby reducing power consumption and write disturb while maintaining reliable write operations on the selected sub-array
Solution Approach 2:
The patent applies different voltage levels to different regions of the memory array during write operations. By carefully controlling the voltage distribution across selected and unselected wordlines and bitlines, the patent minimizes the impact on unselected cells while ensuring successful writes to the target cell
2Reliability
If additional voltage is applied to unselected bitlines to reduce unwanted potentials, then write disturb is reduced, but the problem is passed to unselected cells on those columns and to assignment of voltage in other wordlines
Solution Approach 1:
The patent divides the memory array into multiple sub-arrays that can be independently addressed. This segmentation allows the controller to isolate write operations to specific sub-arrays, reducing the need for complex voltage assignment across the entire array and simplifying the management of unselected cell voltages
Solution Approach 2:
The patent performs preliminary operations such as reading valid pages and identifying invalid pages before executing write operations. This allows the system to prepare the target block in advance, determining which sub-arrays need writing and planning the voltage assignment strategy beforehand, thereby reducing complexity during the actual write operation
3Quantity of substance
If multiple cells are packed in dense cross-point array architectures, then memory density is improved, but memory operations consume high power due to effects on unselected cells
Solution Approach 1:
The patent divides the dense cross-point array into multiple sub-arrays, enabling selective operation on smaller portions of the array. This segmentation maintains the high density advantage while reducing the number of unselected cells affected during write operations, thereby lowering power consumption
Solution Approach 2:
The patent performs write operations on only the necessary sub-arrays containing invalid pages rather than the entire array. By applying write operations partially to only those regions that need updating, the patent reduces power consumption while maintaining memory density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a significant power reduction by optimizing write operations in PRAM, specifically by managing voltage drops across unselected cells, thereby improving energy efficiency and reducing write disturb.
Implementation Method 1
To switch a cell from high to low-resistance state, a high voltage drop is required. The corresponding wordline and bitline are assigned with the required potentials
Implementation Method 2
Phase Change RAM (PRAM) is currently a leading next-memory approach
Data Source
AI summary
A method for performing a write operation in a random access memory (RAM) includes selecting a target block in a RAM with a greatest number of invalid pages, reading valid pages from target block, when a number of invalid pages is greater than a predetermined threshold, performing a bitline-wise block erase of the target block in said RAM, and copying-back valid data to the erased target block in a row-by-row set operation, wherein the erased target block is written with the valid data. Performing the bitline-wise block erase includes sequentially powering on each bitline with a predetermined reset voltage where all other bitlines and wordlines are grounded.