Latent Slow Bit Detection in Non-Volatile Memory
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Solution Overview
Problem
Non-volatile memory (NVM) devices face issues with latent slow-to-erase bits that are difficult to detect, leading to over-erasure and eventual failure, as faster bits become over-erased and slow bits prolong erase operations, causing performance degradation and failure.
Innovation Solution
A method involving reduced bias voltages during test cycles to identify the least erased bit (LEB) and an adjusted erase verify level to determine if it's a statistical outlier, facilitating the detection of latent slow-to-erase bits by distinguishing them from the main distribution of bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard erase bias voltages are applied to erase all cells of an NVM block, then all memory cells are erased, but faster-to-erase cells become over-erased while slower cells extend the erase duration
Solution Approach 1:
The patent applies different erase bias voltage parameters to different subsets of memory cells based on their erase speed characteristics. Fast bits receive reduced erase bias voltages to prevent over-erasure, while slow bits receive standard or enhanced voltages to ensure complete erasure. This parameter differentiation resolves the contradiction by allowing simultaneous optimization of erase completeness and duration.
2Reliability
If soft programming is applied to over-erased cells to correct the issue, then over-erasure problems are addressed, but the process takes relatively long time per address
Solution Approach 1:
The patent performs preliminary classification of memory cells into fast and slow erase groups before the erase operation. By pre-identifying which cells are likely to be over-erased based on historical data or initial characterization, the system can apply appropriate erase voltages from the start, eliminating the need for time-consuming post-erase soft programming operations.
3Productivity
If production testing uses standard verify levels, then most devices pass testing, but latent slow-to-erase bits are not detected until after deployment
Solution Approach 1:
The patent segments the memory block into different erase speed categories (fast bits and slow bits) and applies different verify thresholds to each segment. By comparing actual erase times against expected distributions and applying segment-specific verify levels, the testing process can identify latent slow bits that would otherwise pass standard verification, thereby improving defect detection without significantly impacting throughput.
Data Source
AI summary
In accordance with at least one embodiment, a non-volatile memory (NVM) and method is disclosed for detecting latent slow erase bits. At least a portion of an array of NVM cells is erased with a reduced erase bias. The reduced erase bias has a reduced level relative to a normal erase bias. A least erased bit (LEB) threshold voltage level of the least erased bit (LEB) is determined. An erase verify is performed at an adjusted erase verify read threshold voltage level. The adjusted erase verify read threshold voltage level is a predetermined amount lower than the LEB read threshold voltage level. A number of failing bits is determined. The failing bits are bits with a threshold voltage above the adjusted erase verify level. The NVM is rejected in response to the number of failing bits being less than a failing bits threshold.