Antifuse Memory Array Circuit Architecture for High-Density Programming
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Solution Overview
Problem
Conventional fuse and antifuse technologies in programmable memory devices face challenges such as high current requirements, design complexities, and unintended leakage issues, which affect the yield and reliability of memory arrays.
Innovation Solution
The implementation of an antifuse-based memory array circuit architecture using thick gate PMOS and thin gate NMOS transistors, with a power selector circuit and sense circuitry, reduces current delivery needs and eliminates high-voltage exposure, enabling smaller access transistors and improved bitcell design, thereby enhancing memory array density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fuse links are used with high-current to open-circuit the fuse element, then the fuse can be programmed, but high current requirements and design complexities arise
Solution Approach 1:
The patent extracts the high-current requirement from the programming mechanism by using antifuse links instead of fuse links. The antifuse link breaks down at lower voltages (20-30V) compared to the high currents needed for fuse blowing, thereby removing the complex current delivery infrastructure while maintaining reliable programming capability.
Solution Approach 2:
The patent changes the programming parameter from high current (fuse) to high voltage (antifuse). By using voltage breakdown of the dielectric layer instead of current-induced melting, the design complexity related to current delivery is reduced while achieving reliable one-time programming.
2Ease of manufacture
If antifuse links with thin barrier layers are used to create conductive paths, then programming voltage can be applied, but high-voltage exposure causes unintended leakage and physical damage
Solution Approach 1:
The patent applies local quality by using thick gate oxide in access transistors only where high voltage is applied during programming, while keeping the antifuse link region with thin barrier layer for breakdown. This localized differentiation allows high-voltage programming without damaging other circuit elements, as the thick oxide regions withstand the voltage stress while the thin barrier region undergoes controlled breakdown.
Solution Approach 2:
The thick gate oxide acts as an intermediary protective layer between the high-voltage programming signal and the sensitive thin barrier layer of the antifuse link. During programming, the thick oxide temporarily withstands the high voltage, allowing controlled breakdown of the thin barrier layer while protecting other circuit elements from voltage damage.
3Power
If access transistors are made larger to handle programming currents, then sufficient current drive is achieved, but bitcell area increases reducing memory density
Solution Approach 1:
The patent replaces the mechanical/current-based fuse blowing mechanism with a voltage-based antifuse breakdown mechanism. This substitution eliminates the need for large access transistors to deliver high programming currents, as the antifuse breakdown occurs at voltage thresholds independent of transistor size. Consequently, access transistors can be minimized to only the size needed for normal read operations, significantly reducing bitcell area and increasing memory density.
4Reliability
If conventional fuse programming is used, then one-time programming is achieved, but programming cannot be done before final circuit design is known
Solution Approach 1:
The patent enables preliminary action by allowing antifuse programming to occur before the final circuit design is known. The antifuse links can be programmed during intermediate testing stages or even before final assembly, providing flexibility to modify memory contents based on subsequent design decisions, whereas conventional fuse programming requires final design knowledge beforehand.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in high-density memory arrays with reduced physical damage, improved yield, and efficient multi-bit programming, allowing for better integration in discrete memory devices and on-chip applications like cache repair and encryption key storage.
Implementation Method 1
the gate oxide of the antifuse element breaks down and forms a conductive path between the drain and source
Implementation Method 2
The bitcell configuration includes a thick gate PMOS transistor that blocks high-voltage exposure
Data Source
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AI summary
Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, such as PROM, OTPROM, and other such programmable non-volatile memories. The circuitry employs an antifuse scheme that includes an array of memory bitcells, each containing a program device and an antifuse element configured with current path isolation well and for storing the memory cell state. The bitcell configuration, which can be used in conjunction with column/row select circuitry, power selector circuitry, and/or readout circuitry, allows for high-density memory array circuit designs and layouts.