Memory Device Programming Voltage Ramping

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Solution Overview

Problem

Existing memory device programming techniques, particularly Single-Level Cell (SLC) programming, cause significant stress on memory cells, leading to increased data retention degradation over the life of the memory device.

Innovation Solution

A method of programming memory devices that involves applying a first voltage to a control gate of a selected word line and continuously ramping the voltage to a programming voltage over a duration greater than ten microseconds, followed by holding the voltage at the programming voltage for a shorter duration, without verify operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If SLC programming is used to program memory cells, then programming speed is improved, but data retention degradation increases

Engineering Contradiction:

Improveprogramming speedVSAvoiddata retention

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent changes the voltage ramping parameters by implementing a slow ramp-up phase (first duration greater than 10 microseconds) followed by a brief hold phase (second duration less than the first duration). This parameter modification reduces peak tunneling current while maintaining programming effectiveness, thereby reducing stress on memory cells and improving data retention without significantly impacting programming speed.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If conventional programming pulses are applied to program memory cells, then programming operation is completed, but stress on memory cells increases

Engineering Contradiction:

Improveprogramming operation completionVSAvoidstress on memory cells

Core Design Contradiction:

ProductivityVSStress or pressure

Solution Approach 1:

The patent employs a multi-phase voltage application pattern consisting of a prolonged ramp-up period followed by a shorter hold period. This periodic action structure allows the tunneling current to build gradually during the ramp-up phase, reducing peak current stress on memory cells, and then maintains a controlled current level during the brief hold phase to complete the programming operation.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent modifies the voltage pulse parameters by extending the ramp-up duration (first duration > 10 µs) and reducing the hold duration (second duration < first duration). This parameter change reduces the peak tunneling current and distributes the programming stress over a longer time period, thereby reducing instantaneous stress on memory cells while still achieving complete programming.

Inventive Principle:

Principle #35Parameter changes

3Measurement precision

If verify operations are included in SLC programming, then programming accuracy is improved, but programming time increases

Engineering Contradiction:

Improveprogramming accuracyVSAvoidprogramming time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies a modified programming pulse with extended ramp-up and reduced hold phases that provides sufficient programming accuracy without requiring additional verify operations. The optimized pulse parameters ensure that memory cells are programmed to the correct threshold voltage level directly, eliminating the need for time-consuming verify cycles while maintaining programming precision.

Inventive Principle:

Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces peak tunneling current, minimizes stress on memory cells, and improves data retention by mimicking the slower programming rates of Multi-Level Cell (MLC) operations, thus extending the operational life of the memory device.

Implementation Method 1

The memory cells of a selected word line are programmed to respective data states by applying one or more programming pulses to a control gate of the selected word line in a programming operation to thereby trap electrons in charge-trapping materials of the memory cells

Methodology Applied

Scientific EffectElectron tunneling:

Data Source

PatentUS12205647B2Programming techniques to reduce programming stress in a memory device

Publication Date: 2025.01.21 SANDISK TECHNOLOGIES LLC

AI summary

The memory device includes a plurality of memory cells that are arranged in a plurality of word lines. A controller is provided, and the controller is configured to program the memory cells to respective threshold voltages in a programming operation. The controller is configured to, in the programming operation, apply a first voltage to a control gate of a selected word line of the plurality of word lines. The controller is also configured to continuously ramp a voltage applied to the control gate of the selected word line from the first voltage to a programming voltage over a first duration. The controller is further configured to hold the voltage applied to the control gate of the selected word line at the programming voltage over a second duration that is less than the first duration.