Flash Memory Die Programming Sequence Optimization

Solution Overview

Problem

In conventional flash memory systems, the system controller often waits idle for a substantial period due to the time it takes for a die's cache to release after writing data, which increases transaction time.

Innovation Solution

The proposed solution involves modifying the programming sequence to write data to a lower page of a die before an upper page, leveraging the shorter cache release time for lower pages to reduce waiting time, allowing for sequential data writing that minimizes idle wait periods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is written to upper page of die before lower page in conventional programming sequence, then data integrity is maintained, but system controller must wait idle for substantial period due to cache release time

Engineering Contradiction:

Improvedata integrityVSAvoididle wait time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent inverts the conventional programming sequence by writing data to the lower page of the die first, then to the upper page, instead of the traditional upper-page-first approach. This inversion exploits the shorter cache release time of lower pages to minimize idle wait time for the system controller, while still maintaining data integrity through proper sequencing across multiple dies.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent performs preliminary actions by writing data to lower pages of subsequent dies before completing writes to upper pages of previous dies. This allows the system controller to keep the data bus active and avoid idle waiting, as lower pages have shorter cache release times that enable earlier initiation of subsequent write operations.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If system controller waits for cache release after writing to upper page, then correct programming sequence is maintained, but transaction time increases substantially

Engineering Contradiction:

Improveprogramming sequence correctnessVSAvoidtransaction throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent inverts the conventional programming sequence by writing data to the lower page of the die first, then to the upper page, instead of the traditional upper-page-first approach. This inversion exploits the shorter cache release time of lower pages to minimize idle wait time for the system controller, while still maintaining data integrity through proper sequencing across multiple dies.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent enables continuous useful action by keeping the data bus active throughout the transaction. By writing to lower pages of subsequent dies before completing upper pages of previous dies, the system controller avoids idle waiting and maintains continuous data transfer, thereby improving transaction throughput while ensuring programming correctness through the inverted sequence.

Inventive Principle:

Principle #20Continuity of useful action

3Device complexity

If conventional programming sequence is used with upper page first, then cache management is simplified, but total transaction time increases due to idle waiting

Engineering Contradiction:

Improvecache management complexityVSAvoidtotal transaction time

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The patent inverts the conventional programming sequence by writing data to the lower page of the die first, then to the upper page, instead of the traditional upper-page-first approach. This inversion exploits the shorter cache release time of lower pages to minimize idle wait time for the system controller, while still maintaining data integrity through proper sequencing across multiple dies.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent introduces dynamic sequencing that adapts to the different cache release characteristics of upper and lower pages. By dynamically switching to an inverted write sequence (lower page first) and coordinating writes across multiple dies, the system optimizes transaction time without significantly increasing cache management complexity, as the inversion follows a predictable pattern.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS8397018B2Systems and methods for implementing a programming sequence to enhance die interleave

Publication Date: 2013.03.12 SANDISK TECHNOLOGIES LLC

AI summary

Systems and methods for sequentially writing data to a memory device such as a universal serial bus (USB) memory device are disclosed. A system controller of a memory device including a first die and a second die, each of the first die and the second die including a plurality of pages, writes a first portion of a set of data to a lower page of a second die. The system controller then writes a second portion of the set of data to an upper page of the second die after writing the first portion of the set of data to the lower page of the second die.