Parallelized Multi-Level Program Voltage Verification for SSD Storage

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Solution Overview

Problem

Traditional SSDs consume significant time verifying and adjusting program voltages for different groups of cells to increase storage density, as they require serial verification processes with distinct word line and threshold voltages for each group, leading to inefficiencies in data access and storage capacity utilization.

Innovation Solution

Implementing a parallelized program-verify process where both groups of cells are verified using a single verification word line voltage and threshold comparison, allowing for concurrent verification and determining appropriate program voltages through correlations based on initial pass iterations, thereby reducing the need for repeated setup and teardown of different voltages and comparisons.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If traditional serial verification process is used for each group of cells with distinct word line and threshold voltages, then verification accuracy is maintained, but verification time increases significantly

Engineering Contradiction:
Improveverification timeVSAvoidstorage density increase efficiency
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The patent merges multiple verification operations for different cell groups into a single unified verification process. By combining the verification of first and second groups of cells using a common word line voltage and threshold comparison mechanism, the system reduces the total verification time while maintaining accuracy. This is achieved by performing correlated comparisons across both cell groups simultaneously rather than sequentially.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The verification mechanism is designed to serve multiple cell groups with different threshold levels through a universal verification process. A single word line voltage and threshold comparison setup can verify both the first group of cells (with first threshold level) and the second group of cells (with second threshold level), eliminating the need for separate verification configurations for each group.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If separate verification processes are implemented for different threshold levels, then verification precision is maintained, but device complexity increases

Engineering Contradiction:
Improveverification precisionVSAvoidverification process complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the verification process into correlated comparison stages where different cell groups are verified in relation to each other rather than in isolation. By establishing correlation between the verification of first and second groups of cells, the system maintains precision for each threshold level while using a unified verification framework that reduces overall complexity.

Inventive Principle:
Principle #1Segmentation

3Manufacturing precision

If repeated setup and teardown of different voltages and comparisons is performed, then accurate program voltage determination is achieved, but productivity decreases

Engineering Contradiction:
Improveprogram voltage determination accuracyVSAvoidstorage density increase efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent performs preliminary correlated verification of multiple cell groups using a common reference framework before final program voltage determination. By establishing the correlation between different cell groups in advance through a unified verification process, the system eliminates the need for repeated setup and teardown operations, thereby maintaining accuracy while improving productivity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11004524B2SSD having a parallelized, multi-level program voltage verification
Publication Date: 2021.05.11 INTEL NDTM US LLC
  • US11004524B2 patent drawing
  • US11004524B2 patent drawing
  • US11004524B2 patent drawing

AI summary

An apparatus is described. The apparatus includes a storage device controller having logic circuitry to apply a program voltage verification process for a first threshold level to a group of non volatile memory cells and correlate first program voltages for the group of non volatile memory cells determined from the process to a second threshold level to determine second program voltages for the second threshold level for the group of non volatile memory cells. The second threshold level is higher than the first threshold level.