3D NAND Gate Stack With Upper Separation Regions for Dense Contacts
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity and integration density.
Innovation Solution
A semiconductor device design featuring stacked gate electrodes, channel structures, and contact plugs arranged in specific configurations to enhance integration, including first and second contact plugs separated by upper separation regions, and a data storage system incorporating a semiconductor device with a controller for control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged two-dimensionally, then the device structure is simple, but the data storage capacity is limited
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacked gate electrode structure. Multiple gate electrodes are stacked vertically in the first direction, creating vertical channels that extend through the stack. This dimensional change enables significantly increased storage capacity by utilizing the vertical space above the plate layer rather than only horizontal plane expansion.
2Productivity
If contact plugs are densely arranged to increase integration, then the degree of integration improves, but manufacturing precision requirements increase
Solution Approach 1:
Upper separation regions are introduced as intermediary structures between adjacent first contact plugs. These separation regions extend through the upper gate electrodes and provide physical spacing and isolation between contact plugs. This intermediary structure facilitates easier manufacturing by preventing direct contact between adjacent contact plugs, reducing the precision requirements for contact plug formation while maintaining high integration density.
3Quantity of substance
If gate electrodes are stacked vertically to increase storage capacity, then data storage capacity improves, but device complexity increases
Solution Approach 1:
The gate electrode structure is segmented into multiple distinct components: lower gate electrodes, memory gate electrodes, and upper gate electrodes, all stacked sequentially. This segmentation allows each gate electrode type to serve specific functions within the vertical stack, enabling increased storage capacity through systematic division of the gate structure into functional segments rather than a monolithic design.
Solution Approach 2:
Multiple gate electrodes are nested vertically one above another in the first direction, with channel structures extending through the nested stack. The lower gate electrodes, memory gate electrodes, and upper gate electrodes are positioned in a nested configuration where each layer contributes to the overall storage function, similar to nested dolls where smaller elements are contained within larger structures.
4Ease of manufacture
If first contact plugs are arranged in lines with separation regions between them, then manufacturing ease improves, but device complexity increases
Solution Approach 1:
The upper separation regions automatically provide spacing and alignment between adjacent first contact plugs arranged in lines. The separation regions extend through the upper gate electrodes and create natural boundaries between contact plug positions, enabling the contact plugs to self-align and self-space without requiring complex external positioning mechanisms. This self-service approach simplifies manufacturing by allowing contact plugs to be formed in a systematic linear arrangement with automatic spacing.
Data Source
AI summary
A semiconductor device according to example embodiments of the present disclosure includes: a plate layer, gate electrodes stacked and spaced apart from each other and including lower gate electrodes, memory gate electrodes, and upper gate electrodes, channel structures extending through the gate electrodes, first contact plugs electrically connected to the upper gate electrodes, respectively, second contact plugs extending through portions of the gate electrodes and electrically connected to the memory gate electrodes and the lower gate electrodes, respectively, gate separation regions extending through the gate electrodes, and first upper separation regions extending through the upper gate electrodes between the gate separation regions. Each of the first contact plugs may be in contact with at least one of the first upper separation regions, and the second contact plugs may be spaced apart from the first upper separation regions.