3D NAND Memory Vertical Channels Large Grain Epitaxy
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Solution Overview
Problem
Current three-dimensional NAND memory devices with flat vertical semiconductor channels face challenges in achieving high mobility and efficient manufacturing processes, particularly in forming reliable vertical semiconductor channels with large grain sizes for improved electrical conductivity.
Innovation Solution
The method involves forming alternating stacks of insulating and electrically conductive strips over a substrate with line trenches, where memory stack assemblies and dielectric pillar structures are created, and replacement semiconductor channel layers are grown selectively to form vertical semiconductor channels with an average grain size greater than 20 nm, enhancing mobility and conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing methods are used to form vertical semiconductor channels, then the manufacturing process is simpler, but the grain size is small resulting in low electrical conductivity and mobility
Solution Approach 1:
The patent applies preliminary action by forming a seed layer with large grain size before growing the final semiconductor channel. The seed layer is prepared in advance with optimized crystal structure and grain growth conditions, which then serves as a template for epitaxial growth of the vertical channel, ensuring large grain size is achieved without complicating the overall manufacturing process
Solution Approach 2:
The patent changes physical and chemical parameters during the semiconductor channel formation process, specifically controlling temperature, pressure, and composition gradients during epitaxial growth to promote large grain size formation. By optimizing growth temperature and using appropriate vapor phase deposition parameters, the process achieves high electrical conductivity while maintaining manufacturing feasibility
2Reliability
If smaller grain sizes are used in semiconductor channels, then the manufacturing process is easier, but electrical conductivity and mobility are reduced
Solution Approach 1:
The patent precisely controls grain size by adjusting epitaxial growth parameters including temperature profiles, pressure conditions, and precursor ratios. By maintaining specific temperature ranges and controlling the rate of deposition, the process achieves consistent large grain sizes (greater than conventional dimensions) throughout the vertical channel, ensuring high mobility while maintaining manufacturing precision through parameter optimization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in three-dimensional NAND memory devices with improved electrical conductivity and mobility due to the large grain size of the semiconductor channels, addressing the limitations of existing technologies in this area.
Implementation Method 1
selectively growing replacement semiconductor channel layers from remaining portions of the seed semiconductor material layers to form vertical semiconductor channels
Data Source
AI summary
A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips laterally spaced apart by line trenches, and an alternating two-dimensional array of memory stack assemblies and dielectric pillar structures located in the line trenches. Each of the line trenches is filled with a respective laterally alternating sequence of memory stack assemblies and dielectric pillar structures. Each memory stack assembly includes a vertical semiconductor channel and a pair of memory film. The vertical semiconductor channel includes a semiconductor channel layer having large grains, which can be provided by a selective semiconductor growth from seed semiconductor material layers, sacrificial semiconductor material layers, or a single crystalline semiconductor material in a semiconductor substrate underlying the alternating stacks.