3D NAND Write Voltage Boosting for Threshold Distribution Control
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Solution Overview
Problem
Existing non-volatile semiconductor memory devices face challenges in maintaining a narrow distribution width of threshold values, which affects data retention and reliability.
Innovation Solution
A non-volatile semiconductor memory device with a three-dimensional structure that includes multiple memory cell transistors, each capable of being set to different threshold voltages, and a control circuit that performs specific voltage operations during write operations to manage the distribution width, utilizing a first operation with a reference voltage and subsequent voltage boosts to maintain threshold voltage stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional NAND flash memory is used to increase capacity, then storage density is improved, but threshold voltage distribution width increases
Solution Approach 1:
The patent segments the write operation into multiple sequential steps (first write step, second write step, third write step) with different voltage applications. Each step targets specific memory strings or cell groups, allowing progressive programming that better controls the threshold voltage distribution across the three-dimensional memory structure.
Solution Approach 2:
The patent applies preliminary voltage boosting to selected memory strings before the main write operation. By pre-charging or pre-programming certain cells with elevated voltages in earlier steps, the system prepares the memory state to achieve more uniform threshold voltage distribution during subsequent write operations.
2Reliability
If multiple voltage levels are applied during write operations, then data retention is improved, but device complexity increases
Solution Approach 1:
The patent employs periodic write operations with alternating voltage patterns. Memory strings are programmed in cycles, with different voltage levels applied in alternating steps to different cell groups. This periodic approach ensures thorough programming while distributing the voltage control complexity across multiple manageable phases.
Solution Approach 2:
The patent dynamically adjusts voltage levels and application timing based on the programming progress and target threshold voltage requirements. The control circuit modifies voltage magnitudes and durations in real-time during the write sequence, optimizing data retention while adapting to the changing state of the memory cells.
Data Source
AI summary
A non-volatile semiconductor memory device includes a first semiconductor layer including a first memory cell transistor including a first channel, a second semiconductor layer including a second memory cell transistor including a second channel, a third semiconductor layer including a third memory cell transistor including a third channel, and a control circuit that controls the first memory cell transistor to the third memory cell transistor so that a write operation can be performed. When performing a write operation on the second memory cell transistor, the control circuit supplies a first voltage that is a reference voltage to the second channel, supplies a second voltage that is greater than the first voltage to the first channel, and then supplies the second voltage to the third channel, thereby boosting the voltage supplied to the first channel to a third voltage that is greater than the second voltage.