3D NAND Memory Vpass Disturb Mitigation via Segmented Pass Voltages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face challenges in reducing inadvertent soft-programming of adjacent memory cells during programming operations, known as Vpass disturb, which affects the performance and reliability of the memory device.
Innovation Solution
The proposed solution involves a method for programming memory devices that includes applying different pass voltages to unselected word lines during a programming operation. Specifically, a first pass voltage is applied to first unselected word lines, and a second pass voltage, which can be lower than the first pass voltage, is applied to second word lines corresponding to second memory cells. The second pass voltage can be adjusted based on the position of the selected word line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single pass voltage is applied to all unselected word lines during programming, then the programming operation is simple to implement, but inadvertent soft-programming of adjacent memory cells occurs
Solution Approach 1:
The patent segments the unselected word lines into at least two groups: first unselected word lines receiving a first pass voltage and second unselected word lines receiving a second pass voltage. This segmentation allows different voltage levels to be applied to different groups, preventing inadvertent soft-programming in memory cells adjacent to the selected word line while maintaining operational simplicity through structured voltage application.
Solution Approach 2:
The patent applies different pass voltages to different groups of unselected word lines based on their specific positions relative to the selected word line. The first pass voltage is applied to first unselected word lines while a different second pass voltage is applied to second unselected word lines, creating local quality variations that prevent uniform inadvertent programming across all adjacent cells.
2Quantity of substance
If the number of storage layers and unit storage bits are increased to meet higher storage capacity demand, then storage capacity is improved, but Vpass disturb affecting adjacent memory cells becomes more severe
Solution Approach 1:
The patent segments unselected word lines into multiple groups that receive different pass voltages. By applying a first pass voltage to first unselected word lines and a second pass voltage to second unselected word lines, the patent reduces Vpass disturb in multi-layer storage structures where increased storage capacity would otherwise amplify the harmful effects of uniform pass voltage application.
Solution Approach 2:
The patent changes the pass voltage parameter by applying at least two different pass voltage levels to different groups of unselected word lines. This parameter variation reduces the harmful Vpass disturb effect while accommodating increased storage capacity requirements through multiple storage layers and unit storage bits.
Data Source
AI summary
The present disclosure provides a three-dimensional NAND memory device, comprising a memory array comprising blocks, each block includes first memory cells and second memory cells connected in series to a bit line, a word line driver, and a controller configured to control the word line driver to: performing a programming operation on a memory cell in the first memory cells, the memory cell is controlled by a selected word line of first word lines corresponding to the first memory cells, the first word lines comprising first unselected word lines adjacent to the selected word line, and the performing the programming operation comprises: applying a programming voltage signal to the selected word line to program the memory cell into a target state; applying a first pass voltage to the first unselected word lines; and applying a second pass voltage to second word lines corresponding to the second memory cells.