Read-Only Memories TRIZ Cases

Voltage-sensed clock mode selection lets memory devices switch between parallel and serial timing to ease skew, noise, and power limits.

State splitting simplifies directed-graph branches in constrained data encoding and decoding, reducing hardware complexity while preserving data integrity.

By boosting a selected control voltage, this memory circuit cuts high-voltage switches and area while simplifying multi-voltage selection.

An auxiliary control switch manages the holding path to reduce read voltage drops and power loss in NAND flash current sensing.

A parallel depletion-NFET feedback path fixes startup bias limits so level shifters reach full high output at lower supply voltage.

Bit lines are precharged to peripheral voltage while core-level word and mux signals preserve write margin and cut write power.

A two-step read uses status estimation and coupling group indexing to offset adjacent-cell interference and improve MLC data reliability.

A switched equalization phase lets this current-mode sense amplifier detect small current differences faster while cutting power use.

BTI-induced oxide traps let high-k metal gate MOS cells store data with low-voltage programming, small bitcells, and reversible erase.

A triple-well voltage switch transfers negative and positive word-line voltages to widen threshold margins in NAND flash memory.

Feedback-controlled PMOS and NMOS selection shifts CMOS input threshold to curb inter-symbol interference and cut input current.

Adjustable supply and signal levels let 10-transistor volatile memory cells resist soft errors while preserving write margin and data integrity.

An op-amp-controlled PMOS clamp raises output resistance and sensing margin for more accurate reading of resistance-based memory cells.

When power loss interrupts a write, old and new codeword portions are combined to regenerate ECC bits and preserve non-volatile memory data.

Parity-based data regeneration rebuilds ECC chunks on fewer solid-state storage elements, preserving data integrity after device failures.

A programmable memristive matrix with MIT material reconfigures NDR behavior so one oscillator circuit can generate varied signals.

By raising NAND programming voltage within ECC tolerance, SSDs can write faster early in life without sacrificing data integrity.

Dynamic selection between high- and low-speed buffers lets memory I/O recognize fast signals accurately while minimizing current consumption.

Replacing CMOS pass gates with BEOL MEMS switches shrinks nvSRAM cells, preserves fast read/write, and lowers process cost.

A feedback loop and depletion-mode transistors overcome initial bias limits so the output reaches Vpp even at lower supply voltages.

Selective clock and switching control activates only needed charge pumps, cutting memory voltage-generation current and power use.

Serial CMOS inverters and switched source-substrate bias let low-voltage MOS transistors drive high-voltage memory word lines with less area.

Rapid capacitor discharge through a selected signal path destroys IC elements quickly in a compact circuit for secure data erasure.

An extra block stores new failed column addresses after packaging, extending semiconductor memory reliability and usable life.

Detects interrupted multi-level cell programming and recovers previously written data with adaptive thresholds, reducing backup overhead.

ECC flag cells and ERASE GUARD cells let flash pages switch read modes, preserve bit manipulation, and improve erased-state access.

Feedback-based current or voltage sensing improves memory data-state reads while lowering power use and limiting disturbance to unselected cells.

Two tri-gate non-volatile devices share a current path to shrink FPGA latch area, avoid high-voltage control, and improve state robustness.

Programmable resistive and capacitive clock branches compensate chip-level delay variation, reducing skew and supporting higher IC frequency.

Distributing data and ECC across blocks, pages, chips, and modules improves correction of physically grouped memory errors.

Controllable ECC in an e-fuse one-time program cell array improves read reliability while preserving flexibility for re-programmed data.

An SR flip-flop with switchable delay taps blocks clock glitches without adding fixed signal delay, maintaining timing accuracy across PVT variation.

Predecoders and level shifters support cross-point memory programming while avoiding bulky high-voltage circuitry and excess die area.

Stepwise current control slows the final set-pulse drop in phase change memory, tightening resistance distribution and shortening program time.

Moving-baseline encoding enables drift-tolerant partial erase and rewrite in MLC memory, reducing cell degradation and delaying full erase cycles.

A self-oscillating clock and delay circuit reuses common delay elements to cut lock time and simplify memory data recovery.

Master and slave latches store program and read data together, enabling on-register verification while reducing circuit area and logic overhead.

Inter-die and intra-die slack analysis enables clock-delay repair so weak dies can still operate in a 3D stack and avoid yield loss.

Preloading data into memory socket assemblies enables parallel writing to mounted memory link architectures, cutting configuration time and ROM writer burden.

Mode-based bit line pre-charge slew control cuts capacitive coupling errors and power use while preserving memory read and write speed.

BTI-driven threshold shifts in high-k metal gate MOS cells enable low-voltage non-volatile programming, erasure, and reprogramming.

Stepped gate voltages in pull-up and pull-down driver transistors cut CMOS gate leakage without sacrificing high-speed switching.

After sudden power loss, the controller tests a free NAND flash page, checks ECC errors, and remaps or skips damaged pages to protect data.

Multiple sensing voltages detect threshold drift in flash memory, improving read accuracy and limiting soft data to ECC when needed.

Internal security-event detection and erase control let PLDs automatically zeroize sensitive configuration memory before keys or data are compromised.

ECC-backed erase verification lets NVM tolerate single slow bits, reducing extra erase pulses and extending memory endurance.

Directional current writes latch data into paired nonvolatile cells, enabling power-off retention, fast boot, and lower read leakage.

Phase-change interconnects isolate FPGA programming pulses from logic paths, removing programming-load RC delay while preserving configurable states.

Matched current integration boosts tiny flash bitline and reference current differences for faster, accurate low-voltage sensing.

Boundary-cell +1/-1 markers and recursive propagation cut memory accesses, enabling real-time counter updates at high display resolution.