Nonvolatile Latch Circuit With Directional Memory Write and Fast Boot
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Solution Overview
Problem
Next-generation memory devices require efficient nonvolatile logic circuits that can perform write and read operations without power refresh, ensuring reliable data storage and quick booting without external ROM access.
Innovation Solution
A nonvolatile logic circuit with a latch unit and nonvolatile memory cells, where write operations are performed by supplying current in different directions based on data stored in latch nodes, and read operations involve connecting memory cells to latch nodes when enabled, with auxiliary units for data transmission and equalization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If nonvolatile memory cells are integrated into logic circuits, then data retention without power refresh is improved, but device complexity increases
Solution Approach 1:
The patent combines volatile latch circuits with nonvolatile memory cells into a unified nonvolatile logic circuit structure. The latch nodes are directly coupled to the memory cells, merging the temporary storage function of latches with the permanent storage function of nonvolatile memory, thereby achieving data retention without power refresh while maintaining logic circuit functionality
Solution Approach 2:
The nonvolatile logic circuit structure serves multiple functions: it acts as both a logic circuit for data processing and a nonvolatile memory for data retention. The same circuit structure performs both computational logic operations and long-term data storage, eliminating the need for separate memory components and reducing overall system complexity
2Reliability
If current is supplied to nonvolatile memory cells for write operations, then data storage capability is improved, but power consumption increases
Solution Approach 1:
Write operations to the nonvolatile memory cells are performed periodically or on-demand rather than continuously. The circuit maintains data without power refresh, consuming energy only during write operations and initial power-up, thereby reducing overall power consumption while ensuring reliable data storage
Solution Approach 2:
The nonvolatile memory cells inherently retain data without requiring external power refresh or maintenance operations. Once data is written, the memory cells self-maintain the stored information without consuming additional power, eliminating the need for continuous energy input to preserve data state
3Speed
If nonvolatile memory cells are connected to latch nodes, then data retrieval speed is improved, but leakage current increases
Solution Approach 1:
Transmission gates are used as intermediary components between the nonvolatile memory cells and the latch nodes. These transmission gates act as controlled switches that enable rapid data retrieval when activated while blocking leakage current paths when inactive, thereby achieving fast data access without continuous leakage
Data Source
AI summary
A nonvolatile logic circuit includes a latch unit including a pair of first and second latch nodes; and a pair of first and second nonvolatile memory cells electrically connected to the first and second of latch nodes, respectively. A write operation is performed on the first and second nonvolatile memory cells according to a direction of a current flowing through the first and second nonvolatile memory cells when a write enable signal is activated. The direction of flow of current determined based on data on the respective first and second latch nodes, and a logic value written on the first nonvolatile memory cells is different from a logic value written on the second nonvolatile memory cell.