3D Die Stack Timing Repair Using Inter-Die Slack
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Solution Overview
Problem
Current testing schemes for 3D integrated circuits (ICs) often discard dies that could be usable in a stack due to unnecessary failure rates, as they do not account for the potential benefits of timing differences between dies operated in separate clock domains, leading to inflated costs and waste.
Innovation Solution
A system and method for testing dies in a stack and compensating for delay defects by determining intra-die and inter-die slack values to insert a repair circuit that adjusts the clock signal, allowing defective dies to function within a die stack by borrowing timing margins from available slack paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional at-speed testing is performed on each die individually, then timing delays are detected and defective dies are identified, but the die failure rate is inflated and good dies are unnecessarily discarded
Solution Approach 1:
The testing approach is segmented from individual die testing to stack-level testing. Instead of evaluating each die in isolation, the patent tests dies within the context of a complete stack, allowing timing delays in individual dies to be compensated by timing margins in other dies within the same stack. This segmentation resolves the contradiction by maintaining reliable defect detection while preventing unnecessary discarding of good dies.
Solution Approach 2:
Multiple dies are merged into a single testable unit (stack) rather than testing them separately. The patent combines several dies into a stack configuration where they operate together with shared timing budgets. This merging allows the system to absorb timing variations in individual dies through the collective timing margins of the stack, thereby reducing die failure rate while maintaining testing reliability.
2Manufacturing precision
If dies are tested as stand-alone chips with individual timing budgets, then each die must meet strict timing requirements, but dies with weak defects are unnecessarily discarded when they could function within a stack
Solution Approach 1:
The timing budget parameter is changed from an individual die constraint to a stack-level resource. Instead of each die having a fixed individual timing budget that must be strictly met, the patent implements a shared timing budget across the stack. This parameter change allows dies with weak defects and tighter individual timing margins to be utilized, as their timing constraints are satisfied through the collective timing resources of the entire stack, thereby reducing die waste.
3Reliability
If all dies are tested to ensure individual functionality, then product quality is maintained, but testing costs and complexity increase due to discarding potentially usable dies
Solution Approach 1:
The testing system is made universal by evaluating dies in multiple contexts - both as potential stack components and considering their individual characteristics. The patent implements a multi-functional testing approach that assesses dies for their ability to function within a stack configuration, utilizing shared timing margins and inter-die timing relationships. This universal testing method maintains product quality while reducing complexity by eliminating the need for separate individual die timing budget allocations.
Data Source
AI summary
Systems and methods are disclosed for testing dies in a stack of dies and inserting a repair circuit which, when enabled, compensates for a delay defect in the die stack. Intra-die and inter-die slack values are determined to establish which die or dies in the die stack would benefit from the insertion of a repair circuit.