Shared Delay-Element Clock Architecture for Fast Data Recovery
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Solution Overview
Problem
Traditional data recovery circuits in memory systems rely on separate oscillator and delay-locked loop (DLL) circuits, which can be complex and require time to lock onto reference clock signals, leading to inefficiencies in clock signal generation and data recovery.
Innovation Solution
A clock generation and delay circuit that combines oscillator and DLL functionality, using a self-oscillating design with delay elements arranged in a ring oscillator configuration to generate a reference clock signal and delay clock signals, allowing for immediate locking and efficient data recovery without external reference signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If separate oscillator and DLL circuits are used, then clock signal generation and delay functions are provided, but device complexity increases and locking time is extended
Solution Approach 1:
The patent combines the oscillator and DLL circuits into a single integrated circuit. The oscillator generates a reference clock signal while the DLL delays this signal, and both functions are merged in one device that locks onto the reference clock signal simultaneously, eliminating the need for separate locking processes and reducing overall circuit complexity.
Solution Approach 2:
The integrated circuit performs multiple functions including oscillation generation, signal delay, and clock locking within a single device. This multi-functional design allows the circuit to both generate reference clock signals and provide delayed clock signals for data recovery, reducing the number of components needed while maintaining all necessary functions.
2Device complexity
If separate oscillator and DLL circuits are used, then clock signal generation and delay functions are provided, but the number of components increases
Solution Approach 1:
The patent merges the oscillator and DLL into a single integrated circuit, reducing the total number of components. This integration maintains data recovery reliability because the circuit still provides both the reference clock signal generation and the delayed clock signal output needed for sampling data at optimal timing points.
Solution Approach 2:
The single integrated circuit performs multiple functions that previously required separate components. It generates reference clock signals, delays these signals through multiple delay elements, and provides locked clock outputs for data recovery, all within one component that improves system reliability by reducing inter-component synchronization issues.
3Speed
If traditional oscillator and DLL circuits are used, then clock signals are generated and delayed, but locking time is extended
Solution Approach 1:
By combining the oscillator and DLL in a single circuit, the patent enables simultaneous locking onto the reference clock signal. This eliminates the sequential locking process required by separate circuits, significantly reducing locking time and enabling faster data recovery operations.
Solution Approach 2:
The integrated circuit performs preliminary locking onto the reference clock signal internally, so that when data recovery is needed, the clock signals are already synchronized and ready for immediate use. This preliminary action eliminates the delay that would otherwise occur during the locking process.
4Adaptability or versatility
If separate oscillator and DLL circuits are used, then clock functions are provided, but the system requires external reference clock signals
Solution Approach 1:
The integrated circuit is designed to self-oscillate and automatically lock onto reference clock signals without requiring external control. The oscillator portion generates the reference clock signal internally, and the DLL portion automatically locks onto this signal, enabling the circuit to operate autonomously without external reference signals or complex external circuitry.
Solution Approach 2:
The single integrated circuit provides both self-oscillation capability and DLL functionality, making it adaptable to various applications where external reference clocks may not be available. This multi-functional design allows the circuit to generate its own reference clock while still providing the delay and locking functions needed for data recovery.
Data Source
AI summary
This disclosure provides examples of circuits, devices, systems, and methods for generating a reference clock signal and delaying a received clock signal based on the reference clock signal. In one implementation, a circuit includes a control block configured to generate a control signal. The circuit includes an oscillator configured to generate a reference clock signal. The oscillator includes a plurality of delay elements each configured to receive the control signal and to introduce a delay in the reference clock signal based on the control signal. The delay elements of the oscillator are arranged to generate the reference clock signal. The circuit further includes a delay block configured to receive a clock signal and to generate a delayed clock signal. The delay block includes one or more delay elements each configured to receive the control signal and to introduce a delay in the clock signal based on the control signal.