Flash Memory Page Access Using ECC and Erase Guard Cells
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Solution Overview
Problem
Multilevel flash memory devices face challenges in maintaining reliability and efficiency due to floating gate coupling and the inability to perform bit manipulation, which limits their programmability and data storage capacity, especially when trying to store two bits per cell.
Innovation Solution
The introduction of programmable regions with different data storage densities and reading modes, including an ERASE GUARD cell that determines error correction needs, allows for optimized communication between the memory and microprocessor by enabling bit manipulation and error correction in regions with one bit per cell, while maintaining error correction for erased states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multilevel memory devices store at least two bits per cell to double capacity, then storage density is improved, but bit manipulation capability deteriorates due to parity code constraints
Solution Approach 1:
The memory array is divided into multiple memory regions with different programming capabilities. Some regions are designated as programmable regions that can undergo bit manipulation, while others are non-programmable regions that maintain fixed parity codes for high-density storage. This segmentation allows the system to preserve bit manipulation capability in specific regions while maintaining high storage density in other regions.
2Adaptability or versatility
If repeated programming is allowed in multilevel devices, then adaptability is improved, but reliability deteriorates due to floating gate coupling effects
Solution Approach 1:
Different memory regions are assigned different properties: some regions are optimized for repeated programming with relaxed reliability constraints, while other regions are optimized for high reliability with fixed content. The floating gate coupling effects are localized to specific regions, allowing the system to tolerate repeated programming in certain areas without compromising overall device reliability.
3Ease of operation
If a programmable region with one bit per cell is defined for frequent refresh, then ease of operation is improved, but storage efficiency deteriorates due to half efficiency usage
Solution Approach 1:
The memory system dynamically switches between different reading modes depending on the operational requirements. When bit manipulation or frequent refreshing is needed, the system accesses the programmable region in a first reading mode optimized for these operations. When high-density storage is needed, the system accesses the multilevel region in a second reading mode optimized for storage efficiency, thereby optimizing performance for each specific task.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances memory access efficiency by allowing frequent refresh and improved error correction for regions in erased states, optimizing data storage and reducing the burden of programming steps, thus improving overall memory device performance.
Implementation Method 1
the so called floating gate coupling which causes a widening of the distributions of the read thresholds
Data Source
AI summary
A method for accessing a non volatile memory device including at least one group or sector of memory cells divided into regions programmable with two different data storage densities and accessible with at least two reading modes, for example a two-level mode and a multilevel mode. The memory regions are being organized into pages including a sub-group of memory cells for storing error correction codes of the data stored in the multilevel mode. The method includes providing at the beginning of each page at least one first cell wherein the information concerning the ECC protection or not of the whole page is to be stored. In the sub-group of cells at least one second cell intended for the storage of information concerning the programmed or erased state of the same page is provided. The content of the first and of the second cell is read before accessing, in programming, the corresponding page of the memory region.