Cross-Point Memory Switching Circuitry With Low-Voltage Decoders
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Solution Overview
Problem
Traditional semiconductor memory technologies require significant planar area for decoder circuits and high-voltage circuitry, which limits the efficiency and compactness of non-volatile re-writeable memory systems.
Innovation Solution
The implementation of a two-terminal cross-point memory array with mixed valence conductive oxides and electrolytic tunnel barriers, allowing for voltage-driven conductivity changes without the need for high-voltage circuitry, and the use of predecoders and level shifters to generate necessary voltages within a compatible voltage range for decoder devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional high-voltage circuitry is used to generate programming voltages, then the required voltage range is achieved, but the surface area consumption increases significantly
Solution Approach 1:
The patent extracts and eliminates the high-voltage circuitry from the memory system by using a two-terminal cross-point memory array that operates at lower voltages. The memory cells themselves generate the necessary voltage levels through their structure (mixed valence conductive oxides with electrolytic tunnel barriers), removing the need for separate high-voltage generation circuits and thereby reducing surface area consumption.
Solution Approach 2:
The patent changes the operating voltage parameter from high voltage to lower voltage by using two-terminal cross-point memory cells with mixed valence conductive oxides. These memory cells can be programmed and erased using voltages within the range of existing decoder devices, eliminating the need for high-voltage circuitry and allowing standard CMOS fabrication processes to be used.
2Adaptability or versatility
If decoder circuits are designed to handle block-by-block memory selection, then the memory access capability is achieved, but the planar area required for decoder circuits increases
Solution Approach 1:
The patent transitions from planar decoder circuits to a three-dimensional cross-point memory array structure. The cross-point array uses vertical stacking of conductive oxides and tunnel barriers to achieve memory functionality, effectively moving the storage function from the planar decoder domain to a vertical dimension, thereby reducing the planar area required for decoder circuits.
Solution Approach 2:
The two-terminal cross-point memory cells serve multiple functions: they act as both the memory storage element and the voltage generation element. The mixed valence conductive oxides can be programmed to different resistance states and can also generate the necessary voltage levels for memory operations, eliminating the need for separate high-voltage circuitry and reducing overall circuit area.
3Reliability
If high-voltage circuitry is designed to withstand higher voltages, then the structural integrity is ensured, but the device size increases
Solution Approach 1:
The patent changes the voltage operating parameter from high voltage to lower voltage, allowing the use of standard CMOS fabrication processes and smaller device structures. The two-terminal cross-point memory cells operate within the voltage range that existing decoder devices can handle, eliminating the need for specially designed high-voltage circuitry with larger device dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the size of discrete devices and the overall die size, enabling cost-effective and efficient data storage by allowing smaller, more efficient memory cells and decoders to operate within a smaller voltage range, thereby reducing the need for high-voltage circuitry and minimizing surface area usage.
Implementation Method 1
two-terminal cross-point memory array with mixed valence conductive oxides and electrolytic tunnel barriers, allowing for voltage-driven conductivity changes
Implementation Method 2
two-terminal cross-point memory array with mixed valence conductive oxides and electrolytic tunnel barriers, allowing for voltage-driven conductivity changes
Data Source
AI summary
Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit can include a cross-point memory array formed above the base layer and including re-writable two-terminal memory cells that are configured to operate, for example, within a second voltage range that is greater than the first voltage range. Conductive array lines in the cross-point memory array are electrically coupled with the active devices in the base layer. The integrated circuit also can include X-line decoders and Y-line decoders that include devices that operate in the first voltage range. The active devices can include other active circuitry such as sense amps for reading data from the memory cells, for example.