Memory Write Circuit Using Core-Level Control and Bit-Line Precharge
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Solution Overview
Problem
Modern memory devices face challenges in maintaining correct operation and reducing power consumption when the voltage difference between the core and peripheral voltage domains is large, as existing level shifting mechanisms can lead to significant power consumption and short circuit current paths.
Innovation Solution
The memory device employs access circuitry that asserts word line and mux control signals at the core voltage level while precharging bit lines to the peripheral voltage level, reducing unnecessary power consumption by minimizing the voltage difference across bit lines during write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If level shifting mechanisms are used to pass signals between different voltage domains, then signal transmission between voltage domains is enabled, but power consumption increases and short circuit current paths are created
Solution Approach 1:
The patent introduces a level shifter circuit as an intermediary component that translates control signals from the peripheral voltage domain (VDDP) to the core voltage domain (VDDC). This mediator enables signal transmission between the two voltage domains without requiring the entire access logic circuitry to operate at the higher core voltage, thus reducing overall power consumption while maintaining functionality.
2Use of energy by moving object
If access logic circuitry operates at peripheral voltage level to reduce power consumption, then power consumption is reduced, but write margin becomes insufficient when voltage difference is large
Solution Approach 1:
The patent applies local quality by making different parts of the system operate at different voltage levels. The access logic circuitry operates at the lower peripheral voltage (VDDP) to reduce power consumption, while the level shifter and core voltage domain components operate at the higher core voltage (VDDC) to ensure sufficient write margin. This localized voltage assignment optimizes both power efficiency and write reliability.
Solution Approach 2:
The patent changes the voltage parameter locally within the level shifter circuit, which converts control signals from VDDP level to VDDC level. This parameter transformation enables the control signals to properly drive the core voltage domain circuitry and ensure adequate write margin, while the majority of the system continues to operate at the lower, more power-efficient peripheral voltage.
3Reliability
If all control signals are level shifted to core voltage domain, then write margin is sufficient, but area and power consumption of level shifting circuits increase
Solution Approach 1:
The patent applies partial action by level shifting only the necessary control signals that require core voltage domain operation, rather than level shifting all control signals. Specifically, the level shifter converts signals that directly control memory cell write operations, while other signals remain in the peripheral voltage domain. This selective approach provides sufficient write margin for critical operations while minimizing the area and power overhead of level shifting circuitry.
Data Source
AI summary
A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells.