Memory Clock Mode Configuration for Serial Ring Interfaces
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Solution Overview
Problem
The existing flash memory systems face performance limitations due to signal integrity issues such as crosstalk, signal skew, and simultaneous switching noise, and power consumption increases with higher system clock frequencies, limiting the number of memory devices that can be connected in parallel and requiring additional channels or lower clock frequencies, which increases cost.
Innovation Solution
A semiconductor device with a configurable input circuit that can operate in modes for receiving coincident or non-coincident clock and data edges, and a memory system with a mode setter, clock switch, and configurable data input/output buffer that can switch between parallel and serial clock signals, allowing memory devices to be connected in a serial ring topology for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices are connected in parallel to increase storage capacity, then the available storage capacity increases, but signal integrity deteriorates due to crosstalk, signal skew, and simultaneous switching noise
Solution Approach 1:
The system segments the clock distribution into device-specific clock signals, where each memory device receives its own dedicated clock signal from the memory controller. This segmentation eliminates the shared clock bus that causes signal integrity issues in parallel configurations, allowing multiple memory devices to be connected without crosstalk or signal skew affecting all devices simultaneously.
2Speed
If system clock frequency is increased to improve operation speed, then the operation speed increases, but power consumption increases
Solution Approach 1:
The system implements dynamic clock gating where the memory controller enables clock signals to memory devices only when data transfer is required. During idle periods or when certain memory devices are not actively being accessed, the clock signals are gated off, reducing dynamic power consumption while maintaining high operation speed when needed. This dynamic control allows the system to achieve high speeds on demand without continuously consuming high power.
3Quantity of substance
If the number of memory devices connected in parallel is increased, then the storage capacity increases, but the number of required chip enable signals and clock distribution complexity increases
Solution Approach 1:
The clock distribution is segmented into individual dedicated lines from the memory controller to each memory device. Instead of using a shared clock bus that requires complex synchronization and distribution logic, each device receives its own clock signal, simplifying the overall distribution architecture while enabling support for more memory devices.
4Quantity of substance
If additional channels are added to accommodate more memory devices, then the number of supported memory devices increases, but the device complexity and cost increase
Solution Approach 1:
The memory controller is designed with universal interfaces that can dynamically configure clock and control signal routing to support varying numbers of memory devices. The controller can adaptively manage clock distribution and chip enable signals across different device counts without requiring additional dedicated channels or hardware, thereby supporting more memory devices while maintaining controller simplicity.
Data Source
AI summary
A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.