Dual-Buffer Memory I/O for High-Speed Signal Recognition
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Solution Overview
Problem
Existing buffer technologies either consume excessive current when recognizing high-speed signals or fail to recognize logic levels of high-speed input signals when current consumption is minimized, making it difficult to effectively manage both high and low speed signals in integrated circuits like flash memory.
Innovation Solution
A system that includes both high and low speed buffers, where a controller chip selects the appropriate buffer based on status signals to optimize current consumption and accurate signal recognition, using an I/O channel for signal transfer and a status channel to determine the type of signal, allowing the integrated circuit to switch between buffers depending on the signal type.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high speed type buffer is used to receive a signal input to the I/O pin, then a logic level of the signal can be normally recognized, but a large amount of current is consumed
Solution Approach 1:
The patent implements dynamic buffer selection by introducing a buffer selection unit that switches between high-speed and low-speed buffers based on signal type. The buffer control unit dynamically activates the appropriate buffer (high-speed for data signals, low-speed for command/address signals) based on control signals from the memory controller, thereby optimizing current consumption while maintaining signal recognition accuracy.
2Use of energy by moving object
If a low speed type buffer is used to receive the signal applied to the I/O pin, then current consumption can be reduced, but a logic level of a high speed input signal may not be recognized
Solution Approach 1:
The patent implements dynamic buffer selection by introducing a buffer selection unit that switches between high-speed and low-speed buffers based on signal type. The buffer control unit dynamically activates the appropriate buffer (high-speed for data signals, low-speed for command/address signals) based on control signals from the memory controller, thereby optimizing current consumption while maintaining signal recognition accuracy.
3Adaptability or versatility
If both high-speed and low-speed buffers are present in the integrated circuit, then both high-speed and low-speed signals can be received effectively, but the device complexity increases
Solution Approach 1:
The patent segments the buffer system into distinct high-speed and low-speed buffer units, each optimized for specific signal types. The buffer selection unit segments the control logic to determine which buffer type to activate based on signal characteristics, thereby managing complexity through structured division of functions.
Solution Approach 2:
The buffer system is designed with multi-functionality where the same I/O pin can interface with both high-speed data signals and low-speed command/address signals by dynamically switching between buffer types. The buffer selection unit provides universal control over both buffer types, allowing a single integrated circuit to handle multiple signal types effectively.
Data Source
AI summary
A system includes integrated circuit chip including a first buffer configured to receive signals and a second buffer configured to receive signals, wherein the first buffer receives signals of a higher frequency than the second buffer, a controller chip configured to control the integrated circuit chip, an I/O channel formed between the controller chip and the integrated circuit chip to transfer a first signal and a second speed signal, wherein the first signal has a higher frequency than the second signal, and a status channel formed between the controller chip and the integrated circuit chip to transfer at least one status signal, wherein the integrated circuit chip is configured to select one of the first buffer and the second buffer and actives the selected buffer in response to the at least one status signal and receive a signal transferred through the I/O channel.