MLC Memory Moving-Baseline Encoding for Drift-Tolerant Partial Erase
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Solution Overview
Problem
Multi-level cell (MLC) memory technologies, such as NAND flash and phase-change-memory (PCM), face significant challenges in maintaining data integrity and extending the lifespan of storage devices due to threshold voltage drift and resistance drift, which lead to degradation and reduced endurance during write and erase operations.
Innovation Solution
Implementing threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding, which allows for enhanced data write, read, and partial-erase operations by using a moving baseline to minimize charge transfer and delay full erase cycles, thereby reducing cell degradation and increasing the number of write cycles before full erase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional data write operations are performed on MLC memory, then data is written to the memory cells, but threshold voltage drift and resistance drift cause cell degradation and reduced endurance
Solution Approach 1:
The patent applies preliminary action by performing a read operation before the write operation to detect and compensate for threshold voltage drift or resistance drift that has already occurred. This preliminary detection allows the system to adjust the write parameters in advance, counteracting the drift effects before they cause data integrity issues, thereby extending memory lifespan while maintaining reliability
Solution Approach 2:
The patent changes operational parameters by dynamically adjusting read and write voltage levels based on detected drift conditions. The system modifies voltage parameters adaptively - increasing read voltage to compensate for threshold drift, or adjusting write pulse characteristics based on resistance drift detection - allowing multiple write cycles before full erase while maintaining data integrity
2Reliability
If full erase cycles are performed frequently to maintain data integrity, then data accuracy is preserved, but cell degradation increases and endurance decreases
Solution Approach 1:
The patent applies partial action by performing selective partial erases only on specific memory blocks that have accumulated excessive drift or errors, rather than erasing entire memory arrays. This targeted approach maintains data accuracy in affected areas while minimizing unnecessary degradation from full erase cycles across the entire memory device, thereby extending overall endurance
Solution Approach 2:
The patent implements feedback by continuously monitoring memory cell characteristics through read operations and using this information to determine when and where full erase cycles are truly necessary. The system adjusts erase timing and scope based on actual drift accumulation patterns, performing erases only when data integrity thresholds are approached, thus reducing unnecessary cell degradation while maintaining data accuracy
3Productivity
If threshold voltage drift and resistance drift are not compensated, then operations are simpler and faster, but data integrity deteriorates and memory endurance is reduced
Solution Approach 1:
The patent applies preliminary action by performing a quick read operation before write operations to detect drift conditions. This preliminary detection is fast and does not significantly impact overall operation speed, but it enables subsequent write operations to be adjusted for drift compensation, maintaining data integrity without sacrificing productivity
Solution Approach 2:
The patent changes operational parameters adaptively by adjusting voltage levels and timing based on detected drift conditions. These parameter adjustments are made dynamically but efficiently, allowing the system to maintain high operation speeds while compensating for drift effects through intelligent parameter modification rather than conservative slow operations
Data Source
AI summary
A method and apparatus are provided for implementing enhanced data partial erase for multi-level cell (MLC) memory using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding. A data partial erase for data written to the MLC memory using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding is performed, and a data re-write after the partial erase to the MLC memory is performed using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding. A data partial erase cycle includes a duration and voltage level based upon a degradation of the MLC memory cells.