Dual-Latch Data Register for Integrated Program Verification
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Solution Overview
Problem
Existing anti-fuse memory technologies require a second data register for program verification, leading to increased circuit area and manufacturing costs due to complex logic and verification processes.
Innovation Solution
A dual-function data register integrates program verify operations with data storage functionality, eliminating the need for a second register by using master and slave latching circuits to concurrently store and compare data, thereby simplifying program verification and reducing circuit logic overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a second data register is used for program verification, then program verification can be performed, but circuit area increases and manufacturing costs increase
Solution Approach 1:
The patent combines the program verification function with the existing data register by adding comparison logic that compares data in the master latch with data in the slave latch. This merging eliminates the need for a separate second data register, thereby reducing circuit area while maintaining program verification capability.
Solution Approach 2:
The data register is designed to perform multiple functions: it stores data in the master latch, stores verification data in the slave latch, and performs comparison operations between the two latches. This multi-functionality allows a single register structure to handle both data storage and program verification, reducing the need for additional dedicated verification hardware.
2Reliability
If a second data register is used for program verification, then program verification can be performed, but device complexity increases
Solution Approach 1:
The comparison logic is integrated into the existing data register structure, merging the verification function with the storage function. This integration reduces device complexity by eliminating the need for separate verification logic and reducing the number of independent components that must be designed and manufactured.
3Reliability
If program verification is performed using existing separate verification processes, then verification can be completed, but additional circuit logic is required
Solution Approach 1:
The verification process is merged with the data storage function by using the slave latch to hold verification data and integrating comparison logic directly into the register. This eliminates the need for separate verification circuitry and reduces overall logic complexity.
Solution Approach 2:
The data register performs its own verification function by comparing data in the master latch with data in the slave latch. This self-service capability eliminates the need for external or separate verification processes, reducing circuit logic requirements.
Data Source
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AI summary
A dual function serial and parallel data register with integrated program verify functionality. The master and slave latching circuits of the dual function data register can concurrently store two different words of data. In a program verify operation, the master latch stores program data and the slave latch will receive and store read data. Comparison logic in each register stage will compare the data of both latches, and integrate the comparison result to that of the previous register stage. The final single bit result will indicate the presence of at least one bit that has not been programmed. Automatic program inhibit logic in each stage will prevent successfully programmed bits from being re-programmed in each subsequent reprogram cycle. Either data word can be serially clocked out by selectively starting the shift operations on either the low or high active logic level of a clock signal.