CMOS Input Buffer Threshold Control for Inter-Symbol Interference
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Solution Overview
Problem
In NAND flash memories, the parasitic capacitance at the output node of PMOS and NMOS transistors causes inter-symbol interference, leading to signal deterioration due to the time required to charge/discharge the junction capacitance, especially in high-speed operations and multi-chip packages.
Innovation Solution
An input circuit with a control unit that dynamically adjusts the beta ratio of CMOS inverters by selecting PMOS and NMOS transistors to change the circuit threshold based on feedback signals, reducing the effect of junction capacitance through dynamic control of transistor dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a plurality of CMOS inverters connected in parallel are used as an input buffer to increase operation speed, then the productivity is improved, but the parasitic capacitance at the output node increases causing inter-symbol interference and signal deterioration
Solution Approach 1:
The patent applies dynamics by making the beta ratio of the CMOS inverters adjustable rather than fixed. The control unit dynamically changes the beta ratio by selectively controlling the on/off state of switches connected to the PMOS and NMOS transistors, allowing the input buffer to adapt its characteristics to different operating conditions and reduce inter-symbol interference.
Solution Approach 2:
The patent changes the electrical parameters of the CMOS inverter by adjusting the beta ratio (βp/βn). By controlling the width-to-length ratios of PMOS and NMOS transistors through selective switching, the circuit threshold voltage is modified to optimize signal levels and reduce the harmful effects of parasitic capacitance during high-speed operation.
2Speed
If the beta ratio of CMOS inverters is increased to reduce the effect of junction capacitance, then the speed is improved, but the current consumption increases
Solution Approach 1:
The patent uses dynamics to make the beta ratio adjustable through a control unit that selectively activates switches. This allows the system to optimize the beta ratio for speed when necessary while reducing it during periods when lower current consumption is prioritized, rather than maintaining a constantly high beta ratio.
Solution Approach 2:
The patent modifies the electrical parameters of the CMOS inverter by changing the beta ratio through selective transistor activation. By controlling which PMOS and NMOS transistors are active, the system can adjust the current consumption and speed characteristics to match operational requirements.
3Reliability
If the circuit threshold is adjusted to optimize signal levels, then the reliability is improved, but the device complexity increases due to additional control circuits
Solution Approach 1:
The patent applies segmentation by dividing the control function into separate components: a control unit that receives feedback signals and a feedback unit that monitors output signal levels. This modular approach allows the complex threshold adjustment function to be broken down into manageable segments that can be independently optimized.
Solution Approach 2:
The patent implements feedback by using the output signal level as feedback to the control unit. The control unit adjusts the beta ratio based on this feedback to maintain optimal signal levels, creating a closed-loop control system that automatically compensates for variations without requiring complex external control circuits.
Data Source
AI summary
According to one embodiment, an input circuit includes an input buffer, a control unit, a holding unit, a feedback unit. The input buffer receives a signal input from an outside. The input buffer includes a plurality of CMOS inverters connected in parallel. The plurality of CMOS inverters includes a plurality of PMOS transistors and a plurality of NMOS transistors. The control unit selects one or more PMOS transistors from the plurality of PMOS transistors so as to enter an operable state. The control unit selects one or more NMOS transistors from the plurality of NMOS transistors so as to enter an operable state. The holding unit holds a level of a signal transferred from the input buffer in synchronization with a clock signal. The holding unit outputs the held signal level. The feedback unit feeds the level of the signal output from the holding unit back to the control unit.