MEMS Logic Switches for Compact Non-Volatile SRAM Cells

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Solution Overview

Problem

Current MEMS-based non-volatile memory designs require CMOS devices for peripheral circuits and pass gates, limiting the use of MEMS-only designs, and existing nvSRAM technologies face challenges with speed, endurance, and cost due to large memory cell size and additional process steps.

Innovation Solution

Replacing transistors with MEMS switches in devices like FPGAs, NAND, and nvSRAM, allowing for MEMS-only designs without additional chip layers or FEOL process impacts, and utilizing MEMS switches in SRAM cells to reduce size and cost.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If CMOS devices are used for peripheral circuits and pass gates in MEMS-based NVM, then device functionality is achieved, but chip space efficiency is reduced and manufacturing complexity increases

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidchip structure complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent merges the functionality of CMOS transistors with MEMS switches by integrating the MEMS switch structure directly into the transistor architecture. The MEMS switch replaces the traditional transistor channel, combining mechanical switching with electronic circuit functionality into a single integrated structure, thereby reducing the need for separate CMOS devices and simplifying the overall chip structure.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The MEMS switch is designed to serve multiple functions: it acts as both the switching element and the memory storage mechanism. By making the MEMS device multi-functional, the patent eliminates the need for separate CMOS transistors for switching operations, thereby reducing device complexity and improving chip space utilization.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Area of moving object

If MEMS switches replace transistors in SRAM cells, then memory cell size is reduced, but manufacturing precision requirements increase

Engineering Contradiction:
Improvememory cell areaVSAvoidMEMS fabrication precision
Core Design Contradiction:
Area of moving objectVSManufacturing precision

Solution Approach 1:

The patent employs parameter changes in the MEMS switch design, specifically optimizing the mechanical properties of the cantilever beam and the electrostatic actuation parameters. By carefully tuning these parameters, the patent achieves reliable switching behavior with reduced dimensions, allowing smaller memory cell area while maintaining acceptable manufacturing precision through parameter optimization rather than requiring extreme precision.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If additional process steps are added for nvSRAM functionality, then non-volatile storage capability is achieved, but production cost increases

Engineering Contradiction:
Improvedata retention capabilityVSAvoidproduction cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The MEMS-based nvSRAM design utilizes the inherent mechanical properties of the MEMS switch structure to provide non-volatile storage. The cantilever beam's natural elasticity and the electrostatic actuation mechanism enable data retention without requiring additional complex process steps. The structure essentially serves itself by using its mechanical design to achieve the non-volatile functionality, thereby reducing production costs.

Inventive Principle:
Principle #25Self-service

4Area of stationary object

If MEMS-only design is implemented, then chip space efficiency is improved, but interface design complexity between MEMS and CMOS increases

Engineering Contradiction:
Improvechip area utilizationVSAvoidinterface design complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary read/write circuit that bridges the MEMS switch array and the external interface. This intermediary circuit handles the complex signal conditioning and data latching functions, allowing the MEMS-only memory array to communicate effectively with CMOS logic without requiring complex direct interfaces. The intermediary circuit simplifies the overall system design by isolating the interface complexity from the memory array itself.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables more efficient use of chip space, reduces memory cell size, and lowers production costs by integrating MEMS devices in BEOL processes, while maintaining fast read/write capabilities and non-volatile data storage.

Implementation Method 1

a first micro electromechanical device having a first contact electrode, a first pull-in electrode and a first cantilever electrode movable from a position in contact with the first contact electrode and a position spaced from the first contact electrode

Methodology Applied
Scientific EffectElectrostatic force: Electrostatics

Data Source

PatentUS8203880B2Binary logic utilizing MEMS devices
Publication Date: 2012.06.19 QORVO US INC
  • US8203880B2 patent drawing
  • US8203880B2 patent drawing
  • US8203880B2 patent drawing

AI summary

Embodiments disclosed herein generally relate to switches that utilize micro-electromechanical systems (MEMS). By replacing transistors in many devices with switches such as MEMS switches, the devices may be used for logic applications. MEMS switches may be used in devices such as FPGAs, NAND devices, nvSRAM devices, AMS chips and general memory logic devices. The benefit of utilizing MEMS devices in place of transistors is that the transistors utilize more space on the chip. Additionally, the MEMS devices can be formed in the BEOL without having any negative impacts on the FEOL or necessitating the use of additional layers within the chip.