Feedback Level Shifting Circuit for Low-Voltage High Output
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Solution Overview
Problem
Prior art level shifting circuits face operational failures due to initial voltage biases that prevent the output from reaching the desired high voltage levels, especially when operating voltages are reduced or higher threshold voltage transistors are used, leading to incomplete switching in non-volatile memory devices.
Innovation Solution
The implementation of a level shifting circuit with a feedback loop and additional depletion mode transistors allows for reduced minimum operating voltage requirements and the use of transistors with higher threshold voltages, ensuring reliable operation by adjusting the initial voltage bias conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the minimum operating voltage is reduced or transistors with higher threshold voltages are used, then power consumption is reduced and device reliability is improved, but the output voltage cannot reach the desired high voltage levels due to initial voltage biases
Solution Approach 1:
The patent applies preliminary action by pre-biasing the gate of the depletion mode NFET to Vpp through a connection to the high voltage source. This preliminary voltage establishment ensures that when the enhancement mode PFET turns on, the depletion mode NFET is already in a state that allows it to conduct high voltage current, enabling Vout to reach Vpp levels. The preliminary biasing action prevents the voltage threshold problem from blocking the high voltage output.
Solution Approach 2:
The depletion mode NFET serves as an intermediary device between the enhancement mode PFET and the high voltage source. Unlike enhancement mode transistors that require gate voltage above threshold to conduct, the depletion mode NFET can conduct with zero or negative gate voltage, making it an ideal intermediary that can handle the transition from low voltage control signals to high voltage power delivery without being blocked by threshold voltage limitations.
2Device complexity
If enhancement mode NFETs are used with gates biased to Vcc, then circuit simplicity is maintained, but the initial voltage bias prevents the output from reaching Vpp levels
Solution Approach 1:
The patent applies parameter changes by transitioning from enhancement mode NFET to depletion mode NFET, fundamentally changing the transistor's electrical characteristics. The depletion mode transistor has a different transfer characteristic where it conducts at zero gate voltage and can be turned off by applying a positive gate voltage, whereas enhancement mode transistors require positive gate voltage to conduct. This parameter change in transistor type enables the circuit to achieve Vpp output levels while maintaining relatively simple circuit structure.
Data Source
AI summary
A level shifting circuit having an input and an output where the level shifting circuit is configured to receive a logical high level having a first voltage level at the input and to output a logical high level having a second voltage level at the output where the second voltage level is higher than the first voltage level. Level shifting circuit embodiments having two or more parallel coupled depletion mode transistors coupled to a high voltage source and further coupled to the output by an enhancement mode transistor, and an additional transistor coupled between a first signal and the output of the level shifting circuit where the first signal has the same logic level of the input are disclosed.