NAND Programming Voltage Control for Faster SSD Writes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Solid state drives (SSDs) face inefficiencies in write speed due to over-provisioned error correction codes that provide unnecessary conservative protection during the early life of the device, leading to suboptimal performance despite minimal wear and error rates.
Innovation Solution
Adjusting programming speed by modifying the programming voltage step and exit criteria based on the storage fidelity of NAND memory devices, allowing for increased write speed while ensuring that the error correction code can handle expected errors at the end of life, thus optimizing SSD performance without compromising data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If robust ECC algorithms are provisioned to handle error rates at end of life, then data integrity is guaranteed throughout the SSD's life, but write speed is reduced due to over-provisioned error correction during early life
Solution Approach 1:
The patent applies dynamics by making the ECC algorithm selection adaptive rather than static. The system dynamically switches between different ECC algorithms based on the SSD's operational state (early life vs. end of life), allowing optimal performance at each stage. This resolves the contradiction by enabling fast write speeds during early life when using lighter ECC, while maintaining data integrity at end of life when switching to robust ECC.
Solution Approach 2:
The patent changes the parameter of ECC algorithm strength based on the SSD's age and wear level. By monitoring program/erase cycle count and adjusting the ECC algorithm accordingly, the system optimizes the balance between write speed and data integrity. This parameter change allows the system to use less aggressive ECC during early life for faster writes, while deploying robust ECC at end of life to ensure data integrity.
2Device complexity
If fixed programming speed is used throughout the device life, then simplicity is maintained, but performance is suboptimal during early life when error rates are minimal
Solution Approach 1:
The patent transforms the fixed programming speed into a dynamic parameter that adapts to the SSD's operational stage. By implementing adaptive programming speed based on wear level and error rates, the system achieves optimal performance during early life while maintaining simplicity through automated decision-making. This dynamic adjustment allows faster programming speeds when safe, resolving the contradiction between complexity and productivity.
Data Source
AI summary
Embodiments of the invention describe methods, systems and apparatuses to improve solid state device (SSD) write speed by efficiently utilizing error correction code executed for the device. SSDs may be comprised of several NAND memory devices. It is understood that such devices tend to have a raw bit error rate (RBER) that is related to the program/erase cycle count for the device.Embodiments of the invention efficiently use system ECC by changing the operating conditions of the SSD to better utilize the robustness of the implemented ECC algorithm. For example, embodiments of the invention may alter the programming voltage supplied to an SSD to increase write speed; such an increase may increase the RBER of the device, but will not affect the accuracy of such operations due to the ECC that is provisioned for end of life storage fidelity (i.e., the RBER that will occur at the end of life).