Volatile Memory Cell Voltage Control for Soft Error Immunity
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Solution Overview
Problem
Volatile memory elements in integrated circuits, such as those used in programmable logic devices, are susceptible to soft error upsets caused by cosmic rays and radioactive impurities, leading to data corruption and performance issues, particularly in remote telecommunications equipment where maintenance is burdensome.
Innovation Solution
The implementation of robust memory cells with ten transistors, using adjustable power supply voltages and signal magnitudes during write operations, and body biasing to enhance immunity to soft error upsets, ensuring data integrity and successful data loading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional volatile memory elements (cross-coupled inverters) are used, then the device complexity is low and ease of manufacture is good, but the reliability against soft error upsets is poor
Solution Approach 1:
The memory cell is segmented into multiple functional blocks including storage nodes, access transistors, write control logic, and read control logic. Each segment performs a specific function, allowing the cell to achieve soft error immunity through distributed functionality rather than a simple cross-coupled inverter structure.
Solution Approach 2:
The memory cell performs preliminary actions by pre-charging storage nodes and pre-positioning access transistors in specific states before write or read operations. This preliminary preparation ensures that the cell is in a known good state, preventing soft error upsets from causing incorrect data states.
2Reliability
If robust memory cells with ten transistors are used, then the reliability against soft error upsets is improved, but the ease of manufacture deteriorates
Solution Approach 1:
The invention changes key parameters of the memory cell including transistor count (increased to 10), voltage levels (dual positive power supply voltages), and timing parameters (real-time voltage variation). These parameter changes enable soft error immunity while maintaining compatibility with standard fabrication processes.
Solution Approach 2:
The memory cell employs dynamic voltage adjustment where power supply voltages are varied in real-time during different operational phases. During write operations, one positive power supply voltage is lowered to weaken specific circuitry, and during normal operation, voltages are elevated to strengthen storage nodes, providing adaptive protection against soft errors.
3Reliability
If power supply voltages are varied in real time, then the immunity to soft error upsets is improved, but the use of energy increases
Solution Approach 1:
The memory cell employs periodic voltage adjustment cycles that alternate between write mode (lowered voltage) and read/hold mode (elevated voltage). This periodic switching optimizes energy consumption by using lower voltages during write operations and higher voltages only when necessary for data retention and reading, rather than maintaining high voltages continuously.
Data Source
AI summary
Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array may be adjusted. There may be two positive power supply voltages that are used in powering each memory element. One of the power supply voltages may be temporarily lowered relative to the other power supply voltage to enhance write margin during data loading operations. Other signal strengths that may be adjusted in this way include other power supply signals, data signal levels, address and clear signal magnitudes, and ground signal strengths. Adjustable power supply circuitry and data read-write control circuitry may be used in making these signal strength adjustments.