Configurable Glitch Filter Circuit for Delay-Free Clock Cleaning
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Solution Overview
Problem
Conventional glitch filters in memory devices delay digital logic signals and are sensitive to process, voltage, and temperature variations, failing to provide high accuracy and adaptability in filtering glitches, especially in high-speed memory devices with small package designs.
Innovation Solution
A glitch filter circuit using an SR flip-flop and a configurable delay circuit with switchable taps, allowing dynamic calibration and reconfiguration to maintain a constant delay, independent of glitch width, and block glitches during critical signal transitions, ensuring a glitch-free output clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional de-glitch circuits are used to remove glitches from digital input signals, then glitches are filtered out, but the input signal is delayed by a time greater than or equal to the predetermined de-glitching period
Solution Approach 1:
The patent applies dynamics by making the delay period variable rather than fixed. The delay period is dynamically adjusted based on the amplitude of the input signal, allowing the circuit to adapt its filtering behavior to different signal conditions. This resolves the contradiction by enabling glitch filtering without imposing a constant minimum delay on all signals.
Solution Approach 2:
The patent changes the parameter of delay period from a fixed predetermined value to a variable parameter that depends on signal amplitude. By monitoring the amplitude of incoming signals and adjusting the delay period accordingly, the circuit achieves effective glitch filtering while minimizing unnecessary signal delay for valid transitions.
2Device complexity
If simple delay lines and combinatorial logic are used to filter glitches, then the circuit structure is simple, but the delay line is constant and sensitive to process, voltage, and temperature variations
Solution Approach 1:
The patent implements feedback by monitoring the amplitude of input signals and using this information to dynamically adjust the delay period. This feedback mechanism compensates for variations in process, voltage, and temperature by adapting the delay characteristics in real-time, thereby maintaining measurement precision without significantly increasing circuit complexity.
Solution Approach 2:
The patent transforms the static delay line into a dynamic system that adjusts its delay characteristics based on input signal conditions. This dynamic adaptation allows the circuit to maintain accurate timing despite environmental variations, resolving the contradiction between structural simplicity and measurement precision.
3Device complexity
If Schmidt trigger with predefined hysteresis value is used to filter glitches, then the circuit is simple, but it cannot filter high amplitude glitches beyond its threshold
Solution Approach 1:
The patent applies dynamics by making the filtering threshold variable rather than fixed. Instead of using a predefined hysteresis value, the circuit dynamically adjusts its effective threshold based on the amplitude of incoming signals. This allows the circuit to filter glitches of varying amplitudes while maintaining simplicity in the overall circuit architecture.
Solution Approach 2:
The patent changes the parameter of filtering threshold from a fixed predefined value to a variable parameter that adapts to different signal amplitudes. This enables the circuit to handle both low-amplitude and high-amplitude glitches effectively, expanding its adaptability without significantly increasing circuit complexity.
4Measurement precision
If high speed clock sampling is used to filter glitches, then filtering accuracy is improved, but the sampling clock must be at least ten times faster than input signal which increases device complexity
Solution Approach 1:
The patent changes the parameter of sampling rate from a fixed high-speed requirement to a variable parameter that adapts to the input signal frequency. By using a variable delay period based on signal amplitude rather than requiring a sampling clock ten times faster than the input signal, the circuit achieves effective glitch filtering with reduced clock speed requirements and lower device complexity.
Data Source
AI summary
A glitch circuit includes an SR flip-flop where a received input clock is operatively coupled to set and reset inputs of the flip-flop, respectively. A configurable delay circuit receives an input signal, and an output of the delay circuit provides a delayed signal. The configurable delay circuit includes a plurality of switchable taps, each providing an increment of delay to the input signal. The delay circuit input is operatively coupled to an output of the flip flop, and an output of the delay circuit is operatively coupled to the inputs of the flip-flop. The glitch circuit captures a first signal transition of the input clock and blocks all other transitions from propagating through the flip-flop during a selected delay period so as to provide on an output of the flip-flop, the glitch-free output clock.