High-k Metal Gate MOS Memory Cells Using BTI Threshold Shifts
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Solution Overview
Problem
Conventional metal fuse and antifuse technologies for non-volatile memory devices require high currents and voltages for programming, limiting scalability and security, and do not support multiple levels of programming or erasure.
Innovation Solution
Exploiting bias temperature instability (BTI) effects in high-k/metal gate MOS transistors to induce threshold voltage shifts, allowing for low-power, low-voltage programming and multiple levels of programming, with the ability to erase and reprogram memory cells without physical changes, using NMOS or PMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional metal fuse and antifuse technologies are used for programming memory devices, then non-volatile storage is achieved, but high currents and voltages are required which limit scalability and security
Solution Approach 1:
The patent changes the physical mechanism from destructive fuse blowing or antifuse formation to reversible threshold voltage modulation in high-k metal gate MOSFETs. By utilizing bias temperature instability (BTI) effects, the invention achieves non-volatile storage with low-power programming pulses that modulate the transistor threshold voltage without requiring high currents or voltages, thus resolving the contradiction between reliability and power consumption.
Solution Approach 2:
The patent replaces the mechanical/physical destruction or formation of conductive paths (fuse blowing, antifuse creation) with an electrical field effect mechanism. The high-k metal gate MOSFET threshold voltage is modulated through electrical biasing that exploits BTI effects, substituting the high-power physical modification approach with a low-power electrical control approach that achieves the same non-volatile storage function.
2Adaptability or versatility
If conventional fuse and antifuse links are used, then programming is achieved, but the process is irreversible and does not support multiple levels of programming or erasure
Solution Approach 1:
The patent introduces dynamic reversibility to the programming process by utilizing the controllable nature of threshold voltage in high-k metal gate MOSFETs. The threshold voltage can be modulated forward and backward through applied bias pulses, enabling multiple programming levels and erasure cycles. This dynamic control replaces the static, irreversible state changes of conventional fuses and antifuses, achieving both adaptability and controlled stability.
Solution Approach 2:
The patent employs periodic application of bias pulses to achieve multiple programming levels and erasure operations. By applying sequences of voltage pulses with different polarities and durations, the threshold voltage can be incrementally adjusted to create multiple stable states, enabling multi-level cell (MLC) operation and repeated programming/erasure cycles without degradation.
3Power
If high-k/metal gate MOS transistors are used to exploit BTI effects, then low-power programming and multiple programming levels are enabled, but threshold voltage shifts must be precisely controlled
Solution Approach 1:
The patent implements sense amplifiers and read circuits that detect the threshold voltage state of the high-k metal gate MOSFETs. This feedback mechanism allows the system to accurately determine the programmed state and adjust subsequent programming pulses accordingly, ensuring precise control over threshold voltage shifts despite the complexity of BTI effects. The feedback loop compensates for process variations and ensures reliable multi-level state detection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high-density memory arrays with secure, scalable, and low-power operation, allowing for multiple programming cycles with minimal degradation, and secure storage that is resistant to conventional failure analysis and tampering.
Implementation Method 1
Exploiting bias temperature instability (BTI) effects in high-k/metal gate MOS transistors to induce threshold voltage shifts
Data Source
AI summary
Techniques and circuitry are disclosed for implementing non-volatile storage that exploit bias temperature instability (BTI) effects of high-k/metal-gate n-type or p-type metal oxide semiconductor (NMOS or PMOS) transistors. A programmed bitcell of, for example, a memory or programmable logic circuit exhibits a threshold voltage shift resulting from an applied programming bias used to program bitcells. In some cases, applying a first programming bias causes the device to have a first state, and applying a second programming bias causes the device to have a second state that is different than the first state. Programmed bitcells can be erased by applying an opposite polarity stress, and re-programmed through multiple cycles. The bitcell configuration can be used in conjunction with column/row select circuitry and/or readout circuitry, in accordance with some embodiments.