3D Horizontal Nanosheet Channels With Epitaxial Shell Mobility Tuning
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Solution Overview
Problem
The challenge in semiconductor device fabrication is to overcome scaling limitations in planar devices by increasing transistor density in three-dimensional (3D) integration, which is difficult to achieve in logic chips compared to flash memory applications, and to enhance the performance of transistors in 3D configurations.
Innovation Solution
The method involves forming vertically stacked transistors with alternating horizontal layers, where epitaxially grown shells optimize channel structures for both N-type and P-type transistors, enabling lateral gate-all-around channel transistors with separate control of gate electrodes and channel materials, allowing for dual channel release options and high mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are stacked vertically in 3D configuration, then transistor density is increased, but device performance and mobility are degraded
Solution Approach 1:
The patent transitions from planar 2D transistor channels to three-dimensional nanosheet structures with vertical stacking. The channel extends in multiple dimensions (horizontal length, vertical thickness, and lateral wrap-around), enabling higher density while maintaining performance through the gate-all-around configuration that controls the channel from all directions.
Solution Approach 2:
The gate electrode completely surrounds the nanosheet channel in a nested configuration, with the gate wrapping around the channel from all lateral directions. This gate-all-around structure provides superior electrostatic control over the channel compared to conventional planar gates, enabling high-performance 3D transistors.
2Ease of manufacture
If uniform channel material is used in 3D nanosheets, then fabrication is simplified, but mobility optimization for both NMOS and PMOS is limited
Solution Approach 1:
The patent implements different semiconductor materials in different regions of the alternating layer stack. Specific layers are designated as n-type channel material for NMOS transistors while other layers use p-type channel material for PMOS transistors. This local material differentiation enables optimal mobility for both device types while maintaining the simplicity of alternating layer fabrication.
Solution Approach 2:
The nanosheet structure employs composite material composition with alternating layers of different semiconductor materials. The stack includes n-type semiconductor layers, p-type semiconductor layers, and sacrificial layers, creating a composite structure that enables both NMOS and PMOS functionality with optimized mobility for each device type.
3Reliability
If planar 2D transistor configuration is used, then device performance is maintained, but scaling and density are limited
Solution Approach 1:
The patent employs vertical stacking of multiple nanosheet transistors in the third dimension, transitioning from planar 2D arrangement to 3D configuration. Multiple transistor channels are stacked vertically, enabling higher density while the gate-all-around structure maintains performance by providing complete electrostatic control of each channel.
Solution Approach 2:
The alternating layer stack is segmented into multiple discrete nanosheet channels separated by sacrificial layers. Each nanosheet forms an independent transistor channel that can be individually controlled by the gate electrode, enabling multiple transistors to be stacked vertically while maintaining performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly boosts transistor mobility and density, enabling high-performance 3D nanosheets with optimized material selection for both NMOS and PMOS devices, facilitating advanced 3D integration in logic chips beyond the limitations of planar devices.
Implementation Method 1
forming a first shell on a first one of the uncovered second layers, the first shell and the first one of the uncovered second layers forming a first channel structure
Data Source
AI summary
Aspects of the present disclosure provide a method of fabricating a semiconductor device including a plurality of vertically stacked transistors. For example, the method can include providing a vertical stack of alternating horizontal first and second layers, the second layers forming channels of the transistors. The method can further include uncovering the second layers. The method can further include forming a first shell on a first one of the uncovered second layers, the first shell and the first one of the uncovered second layers forming a first channel structure of a first one of the transistors.