Transistor TRIZ Cases

A backside trench capacitor and back wiring network cut voltage drop and power supply noise in highly integrated semiconductor power delivery.

A stacked sub-substrate and insulating layer block charge transfer between pixel photodiodes, improving signal-to-noise ratio and conversion gain.

A split N+ cathode-gate layout blocks shunt current in SCRs, improving noise immunity and reducing false triggering under voltage noise.

Header and footer gate transistors isolate VDD and VSS in BSPDN logic, cutting standby leakage without sacrificing nanosheet CMOS scaling.

A recessed gate dielectric and sidewall spacer layout helps integrate MV and LV MOSFETs on one wafer without gate loss during planarization.

An in-situ gate driver powered by the GaN device cuts parasitic noise, avoids external supplies, and improves CMTI in cascode switching.

Separating source and drain contacts into different layers creates a vertical oxide TFT channel that cuts area and parasitic capacitance in displays.

Switchable current sources bias MOSFET body and source nodes to cut ON resistance and suppress OFF leakage in high-voltage bidirectional switches.

A gate driver with RC delay and variable resistance clamps FET gate voltage to limit inrush current across wide battery input ranges.

Bottom-up selective Si/SiGe nanowire removal and sub-fin isolation adjust channel density, tune drive current, and limit leakage at sub-10 nm.

Different fin spacer heights and recess depths control FinFET epitaxial source/drain growth, prevent merging, and lower contact resistance.

Stored charge powers the control circuit so vehicle capacitance can discharge safely after HV disconnect, even if external power fails.

Vertical stacking with a shared gate and oxide semiconductor films shrinks pixel transistor area while preserving fast switching and aperture ratio.

Pulsed-bias plasma etching forms a W-shaped FinFET source/drain recess that guides merged epitaxy, lowers parasitic capacitance, and preserves contact area.

A masked work function layer etch protects gate dielectrics and fins, cutting leakage and improving gate resistance in scaled FinFETs.

A buried power rail contact placed between VFET source/drain regions cuts MOL resistance while preserving density and short-channel control.

Partition structures in the isolation region rebalance ballasting resistance, preventing premature finger triggering in high-voltage ESD protection.

Epitaxial shells on stacked horizontal nanosheet channels raise transistor density while preserving NMOS and PMOS mobility in 3D logic.

Sacrificial spacer removal creates sealed air gaps between the gate and source/drain contacts to lower stray capacitance in scaled transistors.

A PDMS micro-stamper transfers selected 2D flakes with precise alignment while avoiding cross-contamination and damage to nearby devices.

Integrated level shifters and dead-time control help a monolithic GaN half-bridge prevent shoot-through while supporting efficient high-frequency conversion.

Using spaced epitaxial regions and graded impurity zones, this SOI resistor raises resistance without enlarging chip area.

A same-row pixel output line arrangement cuts capacitive crosstalk, preserving image quality at higher readout speeds.

A stepped HEMT channel uses a thicker region away from the gate to cut channel resistance and improve output charge in high-frequency circuits.

Mandrel and dummy-fin patterning creates non-uniform fin pitch, raising semiconductor integration density without excessive pitch-control complexity.

Varying isolation depth by voltage region raises breakdown and threshold voltage while keeping semiconductor structures compact and manufacturable.

A split buried word line places one conductive layer below the doped region to curb GIDL, row hammer, and DRAM refresh leakage.

Pre-spacer gate cuts enable narrower poly patterning in gate-all-around structures while preserving gate height, overlay control, and transistor density.

Multiple diode and SCR discharge paths limit ESD overshoot, cut voltage drop, and lower parasitic capacitance at high-speed I/O pads.

A fin-shaped source/drain contact with upper and dummy contact regions improves current control and suppresses short-channel effects.

A self-powered gate driver harvests switching energy to stabilize GaN cascode midpoint voltage, cut parasitic loss, and simplify hardware.

Two lower-aspect-ratio front and back contact plugs replace one deep via, reducing fill defects, resistance, and parasitic capacitance.

An inverted-T outer gate dielectric with inner and outer electrodes helps stacked MOSFETs keep electrical control and reliability at higher density.

Multi-cycle dep-etch epitaxy restrains lateral source/drain growth in FinFETs, preventing merging while preserving contact volume and CD uniformity.

Layer transfer and low-temperature epitaxy enable monocrystalline bottom-gate 3DIC transistors with higher mobility, lower leakage, and tighter alignment.

Overlapping conductive layers and oxide source-drain regions stabilize flexible oxide TFTs for faster driving circuits and lower leakage.

Laterally staggered IC interconnect traces preserve via overlap and end spacing while reducing parasitics and easing 3D routing constraints.

Asymmetrical gate heights and isolated active regions improve FinFET transistor control, electrical isolation, and circuit reliability.

A nitride-based passivation layer blocks etchant reactions that cause blisters, improving FinFET threshold voltage control.

A self-aligned gate lands on isolation beside an epitaxial fin to limit sub-fin coupling, reducing parasitic capacitance and leakage.

A bi-layer T-shaped liner helps equalize FinFET gate etching, protect spacers, and reduce loading and parasitic capacitance.

Photoelectric data is converted into spike pulses for low-noise readout and on-chip neural processing, cutting transfer load and power use.

Capacitive coupling in an oxide semiconductor memory circuit generates higher write voltages from one supply, cutting level shifters, area, and power.

Charged dielectric wall sections in fork-sheet FETs repel carriers to cut leakage, strengthen gate control, and reduce DIBL.

A dielectric liner at stacked fin ends prevents over-etching, cuts spacer voids, and improves gate formation and nanosheet uniformity.

Backside source/drain contacts in a fin-type active region cut wiring resistance and parasitic capacitance while preserving dense IC layout.

A wraparound gate on a vertical GaN channel evens the electric field to raise breakdown voltage, cut leakage current, and improve switching behavior.

Alternating stacked capacitor electrodes and isolated side vias raise IC capacitance density while reducing deposition and etching variation.