Gate-All-Around Cut Gate Layout for Narrow Poly Patterning
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Solution Overview
Problem
The challenge in integrated circuit fabrication lies in achieving precise patterning of narrow poly cuts in gate-all-around structures, particularly at the nanoscale, where conventional methods face difficulties in maintaining gate height and requiring complex lithographic processes, leading to trade-offs between feature size and spacing, which affects transistor density and performance.
Innovation Solution
The implementation of a pre-spacer-deposition cut gate approach, where narrow poly cuts are performed after hardmask patterning or poly etch, allowing for independent Si removal and maintaining gate height, with mask splitting techniques to facilitate both narrow and wide cuts, enabling more cost-effective and scalable processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If narrow poly cuts are attempted at a later stage of the process flow, then transistor density can be increased, but lithographic overlay tolerances are lost and manufacturing precision deteriorates
Solution Approach 1:
The patent applies preliminary action by forming the poly gate cut early in the process flow before spacer deposition, rather than attempting narrow cuts at a later stage. This preliminary cut is made when lithographic overlay tolerances are still maintained, and subsequent spacers are deposited to define the final narrow transistor dimensions, thus achieving high transistor density without sacrificing manufacturing precision
Solution Approach 2:
The patent segments the gate formation process into distinct steps: first forming the poly gate with relaxed overlay tolerances, then depositing spacers to define the final narrow transistor dimensions. This segmentation allows each step to be optimized independently - the poly cut for manufacturability and the spacer deposition for precision dimensional control
2Ease of manufacture
If conventional poly cut processes are used, then process flow simplicity is maintained, but desirable fin stress is lost and transistor performance deteriorates
Solution Approach 1:
The poly gate cut is performed as a preliminary action early in the process flow when the fin structure is still intact and can withstand the cutting process. This preliminary cut establishes the gate position while preserving fin stress characteristics, and subsequent spacer deposition and etching steps complete the narrow transistor formation without compromising the fin stress that was maintained during the preliminary cut
Data Source
AI summary
Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.