DRAM Active Region Recess Layout for Bit Line Isolation
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Solution Overview
Problem
As semiconductor memory devices, particularly DRAMs, shrink in size, maintaining electrical isolation between bit lines and storage nodes becomes increasingly challenging, leading to leakage issues that can cause device failure.
Innovation Solution
A method is developed to form a DRAM device with a larger manufacturing process window by creating island features on a substrate to protect terminal portions of active regions during etching, allowing for uniform etching of central portions and preventing direct contact between bit lines and storage nodes, using a series of etching and spacer formation steps to ensure isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory cell size is shrunk to increase integration density, then the productivity and integration density are improved, but the electrical isolation between bit lines and storage nodes deteriorates, leading to leakage issues
Solution Approach 1:
The active region is segmented into terminal portions and central portions by word lines. The terminal portions are selectively recessed to form storage node contacting regions, while the central portions remain at the original surface level to form bit line contacting regions. This segmentation allows bit lines to contact only the central portions at a higher elevation, physically isolating them from storage nodes located in the recessed terminal portions, thereby maintaining electrical isolation while achieving high integration density.
Solution Approach 2:
The invention introduces a vertical dimension to the isolation structure by selectively recessing the terminal portions of active regions while keeping the central portions at the original surface level. This creates a height difference (elevation) between the bit line contacting regions and storage node contacting regions, adding a vertical separation dimension that effectively prevents leakage between bit lines and storage nodes even when lateral dimensions are shrunk for higher integration density.
2Ease of manufacture
If conventional etching methods are used without selective recessing, then the manufacturing process is simpler, but the uniformity of recessed depths and process window are insufficient, leading to leakage between bit lines and storage nodes
Solution Approach 1:
Word lines are formed in advance to divide the active regions into terminal portions and central portions before the etching process. These pre-formed word lines serve as etching stop layers that automatically define the boundaries between regions to be recessed and regions to remain at original level. This preliminary action ensures uniform recessed depths and a larger process window, as the etching process naturally stops at the word line interface, preventing over-etching and leakage.
3Reliability
If bit lines are formed to traverse through active regions, then the electrical connection is improved, but the direct contact between bit lines and storage nodes increases, causing leakage
Solution Approach 1:
Different regions of the active structure are given different local qualities: the central portions are maintained at the original surface level to form bit line contacting regions with good electrical connection, while the terminal portions are selectively recessed to form storage node contacting regions. This local differentiation allows bit lines to make excellent electrical contact with central portions while the recessed terminal portions remain isolated, preventing leakage between bit lines and storage nodes.
Data Source
AI summary
A method for forming a memory device includes the steps of providing a substrate, forming an isolation structure in the substrate to define a plurality of active regions in the substrate, the active regions respectively comprising two terminal portions and a central portion between the terminal portions, forming a plurality of island features on the substrate, wherein each of the island features covers two of the terminals portions respectively belonging to two of the active regions, performing a first etching process, using the island features as an etching mask to etch the substrate to define a plurality of island structures and a first recessed region surrounding the island structures on the substrate, and removing the island features to expose the island structures.