Oxide TFT Vertical Channel Layout for Smaller Display Pixels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current oxide Thin Film Transistors (TFTs) occupy large area due to the required distance between source and drain contact through-holes, leading to parasitic capacitance and suboptimal display performance in LCD and OLED display apparatus.
Innovation Solution
The source and drain of the TFT are formed in different layers, allowing for a vertical channel configuration, reducing channel length and area occupancy, and enabling the gate and drain/source to be formed in the same layer to minimize parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If source contact through-hole and drain contact through-hole are formed in the same layer, then the etching process can be simplified, but the required distance between them increases the TFT area
Solution Approach 1:
The patent transitions from a planar configuration where source and drain contact holes are formed in the same layer to a stacked configuration where source contact hole is formed in the first insulating layer and drain contact hole is formed in the second insulating layer. This dimensional change allows both contact holes to be formed in different vertical levels, eliminating the need for lateral spacing while simplifying the etching process.
2Adaptability or versatility
If gate is formed in a different layer from source and drain, then the transistor structure is more flexible, but parasitic capacitance is generated between gate and source/drain
Solution Approach 1:
The patent merges the gate with the drain electrode by forming them in the same second insulating layer. This consolidation eliminates the lateral separation between gate and drain, thereby removing the parasitic capacitance pathway while maintaining the vertical channel structure and structural flexibility.
3Reliability
If required distance is maintained between source contact through-hole and drain contact through-hole, then TFT can function properly, but the size of oxide TFT becomes relatively large
Solution Approach 1:
The patent resolves the area constraint by moving the contact holes to different vertical dimensions. The source contact hole penetrates the first insulating layer while the drain contact hole penetrates the second insulating layer, allowing both contacts to be formed without lateral spacing requirements, thus maintaining TFT functionality while minimizing device area.
Data Source
Figure 1~3
Figure 3a~3g
Figure 4a~4g
AI summary
A thin film transistor comprises: a source(1) over a substrate(10); a first insulation layer(2) having a source contact through-hole corresponding to a position of the source(1) over the source(1); an active layer(3) electrically connecting with the source(1) through the source contact through-hole over the etching stop layer; a second insulation layer(4) having a drain contact through-hole exposing a portion of the active layer(3) over the active layer(3); and a drain(5) electrically connecting with the active layer(3) through the drain contact through-hole over the second insulation layer(4).