Nanostructure FET Inner Spacer Formation for Source/Drain Protection
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Solution Overview
Problem
The formation of inner spacers in semiconductor devices, particularly in nanostructure channel FETs, has not been entirely satisfactory in protecting the source/drain structure from damage during the gate replacement process, leading to inefficiencies and potential performance issues.
Innovation Solution
A method is introduced where a passivation layer is formed on the sidewall surfaces of the first semiconductor layers using a plasma treatment, allowing for selective deposition of dielectric spacers between the second semiconductor layers, which enhances gap fill capability and minimizes damage to the spacers during subsequent removal processes, thereby reducing parasitic fringing capacitance and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional inner spacer formation is used, then the source/drain structure is protected to some extent, but the spacers still suffer from damage during gate replacement and gap fill capability is insufficient
Solution Approach 1:
A passivation layer is formed on the sidewall surfaces of the first semiconductor layers before the dielectric spacer deposition. This preliminary protective action prevents damage to the inner spacers during subsequent gate replacement processes while the dielectric spacers are formed in the cavities between the second semiconductor layers
Solution Approach 2:
The passivation layer acts as an intermediary protective barrier between the sidewall surfaces and the dielectric spacer material. This intermediary layer enables selective deposition of dielectric spacers with enhanced gap fill capability while minimizing direct contact and potential damage between the spacer material and the semiconductor structure
2Reliability
If dielectric spacers are formed to protect source/drain regions, then protection is provided, but parasitic fringing capacitance remains significant
Solution Approach 1:
The dielectric spacers are selectively formed in the cavities between the second semiconductor layers at specific locations where parasitic capacitance is most problematic. The passivation layer is selectively formed on sidewall surfaces, creating localized protection zones that reduce fringing capacitance precisely where needed without adding unnecessary material elsewhere
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces damage to the inner spacers and enhances the gap fill capability of the dielectric spacers, leading to improved performance and reliability of nanostructure FETs by minimizing parasitic fringing capacitance and protecting the source/drain regions.
Implementation Method 1
a passivation layer is formed on sidewall surfaces of the first semiconductor layers by a plasma treatment
Data Source
AI summary
Embodiments of the present disclosure provide a method for forming a semiconductor device structure. In one embodiment, the method includes forming a fin structure having first semiconductor layers and second semiconductor layers alternatingly stacked, removing edge portions of the second semiconductor layers to form cavities between adjacent first semiconductor layers, selectively forming a passivation layer on sidewalls of the first semiconductor layers, forming a dielectric spacer on sidewalls of the second semiconductor layers and filling in the cavities, wherein the passivation layer is exposed. The method also includes removing the passivation layer, and forming an epitaxial source/drain feature so that the epitaxial source/drain feature is in contact with the first semiconductor layers and the dielectric spacers.