FinFET Work Function Layer Patterning Without Dielectric Damage
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in forming reliable semiconductor devices at increasingly smaller sizes, where the complexity of fabrication processes increases due to decreasing feature sizes, leading to difficulties in achieving reliable FinFETs with minimal gate leakage current and optimal gate resistance.
Innovation Solution
The process involves forming fin structures on a substrate, depositing isolation and dummy gate layers, performing anisotropic etching to create spacers, and carefully managing the etching depth of mask layers to prevent over-etching and damage to gate dielectric layers, while ensuring adequate filling of gate electrodes in trenches of varying widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process complexity increases and device reliability becomes difficult to achieve
Solution Approach 1:
The gate structure is segmented into multiple functional layers: gate dielectric layer, work function layer, and gate electrode layer. This segmentation allows each layer to be optimized independently for its specific function, enabling reliable device operation at smaller feature sizes while maintaining production efficiency
Solution Approach 2:
Different materials are used at different locations within the gate structure to provide local quality optimization. The gate dielectric layer uses high-k material for electrical isolation, the work function layer uses specific materials (tantalum, titanium, or tungsten) for work function control, and the gate electrode uses conductive materials for current conduction, thereby achieving reliable device performance at scaled dimensions
2Ease of manufacture
If conventional gate structures are used at smaller sizes, then manufacturing is simpler, but gate leakage current increases and gate resistance becomes suboptimal
Solution Approach 1:
The work function of the gate is adjusted by selecting specific materials for the work function layer (tantalum, titanium, or tungsten) based on the desired transistor type (n-type or p-type). This parameter change enables optimal threshold voltage control and reduced gate leakage current while maintaining ease of manufacture through standard deposition processes
Solution Approach 2:
The gate structure employs composite materials combining gate dielectric (high-k material), work function layer (tantalum, titanium, or tungsten), and gate electrode materials. This composite structure achieves optimal electrical characteristics including reduced gate leakage current and controlled gate resistance while remaining manufacturable
3Manufacturing precision
If etching depth is increased to fully expose features, then patterning completeness improves, but gate dielectric layers and fin structures suffer damage
Solution Approach 1:
A mask layer is formed over the gate dielectric layer and fin structures before the etching process. This preliminary protective action prevents direct exposure of the gate dielectric to harsh etching conditions, allowing complete pattern transfer without damaging the underlying sensitive structures
Solution Approach 2:
The mask layer acts as an intermediary between the etching process and the gate dielectric layer. It absorbs the mechanical and chemical stress of the etching process, enabling complete patterning while protecting the gate dielectric from damage through this intermediate protective layer
4Device complexity
If mask layers are removed completely after etching, then process simplicity increases, but gate dielectric layers become exposed to damage
Solution Approach 1:
The mask layer is formed in advance to provide continuous protection over the gate dielectric layer and fin structures throughout the etching process. This preliminary protective measure ensures that even after etching completion, the gate dielectric remains protected without requiring additional protective steps, balancing process simplicity with structure protection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces gate leakage current and improves gate resistance by protecting gate dielectric layers and fin structures from damage, facilitating the formation of functional FinFETs with enhanced performance.
Implementation Method 1
performing anisotropic etching to create spacers
Implementation Method 2
depositing isolation and dummy gate layers
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate. The method includes forming a dielectric layer over the substrate, the first fin structure, and the second fin structure. The method includes forming a first work function layer in the first trench and the second trench. The method includes forming a first mask layer over the first work function layer in the first trench. The method includes removing the first work function layer exposed by the first mask layer. The method includes removing the first mask layer. The method includes forming a first gate electrode in the first trench and a second gate electrode in the second trench. The method includes forming a first hard mask layer in the first trench and a second hard mask layer in the second trench.