BJT ESD Protection Circuit Holding Voltage Adjustment

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Solution Overview

Problem

Traditional ESD protection circuits have a low holding voltage, leading to latch-up issues and require a large layout area, which are not effectively addressed by existing stacked ESD devices.

Innovation Solution

An ESD protection circuit using a bipolar junction transistor (BJT) with a trigger source, where the collector is connected to a high voltage power line and the emitter and base to a low voltage power line, allowing the holding voltage to be adjusted by modifying the base width of the BJT, thus preventing latch-up and reducing layout area requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a traditional ESD protection circuit is used, then the layout area is small, but the holding voltage is low causing latch-up issues

Engineering Contradiction:

Improveholding voltageVSAvoidlayout area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent changes the fundamental parameter of the protection circuit by replacing the traditional MOS-based structure with a bipolar junction transistor (BJT) structure. This parameter change enables the holding voltage to be determined by the BJT's base width rather than by stacked transistor configurations, thereby increasing holding voltage without proportionally increasing layout area.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent substitutes the traditional MOS transistor mechanism with a BJT mechanism. The BJT's current amplification特性 and base-width-controlled holding voltage replace the stacked MOS transistor approach, achieving higher holding voltage with reduced area complexity.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If a stacked ESD device is used to increase holding voltage, then latch-up is prevented, but the layout area increases due to multiple transistors

Engineering Contradiction:

Improvelatch-up preventionVSAvoidlayout area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent changes the structural parameter from multiple stacked transistors to a single BJT with controlled base width. The holding voltage is adjusted by modifying the base width dimension rather than by increasing the number of stacked devices, thereby preventing latch-up while minimizing layout area expansion.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

Instead of increasing holding voltage by stacking transistors vertically (adding more layers), the patent adjusts the base width dimension of the BJT horizontally. This dimensional approach achieves the same voltage control function with reduced overall device footprint.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10262987B2Electrostatic discharge protection circuit

Publication Date: 2019.04.16 UNITED MICROELECTRONICS CORP

AI summary

The present invention provides an ESD protection circuit electrically connected between a high voltage power line and a low voltage power line, and the ESD protection circuit includes a bipolar junction transistor (BJT) and a trigger source. A collector of the BJT is electrically connected to the high voltage power line, and an emitter and a base of the BJT are electrically connected to the low voltage power line. The trigger source is electrically connected between the base of the BJT and the high voltage power line.