Semiconductor Isolation Layout for High Breakdown Voltage Scaling
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Solution Overview
Problem
The manufacturing of integrated-circuit semiconductor devices with transistors for different voltage ranges is complex, leading to issues such as low breakdown voltage and increased yield loss, as standard isolation processes are not suitable for miniaturized semiconductor structures, and the size of high-voltage devices becomes too large when trying to meet high breakdown voltage requirements.
Innovation Solution
A semiconductor structure is developed with varying isolation depths depending on the voltage region, featuring deeper isolations in high-voltage regions and shallower isolations in low-voltage regions, achieved by adding a photolithography and etching process to existing manufacturing methods, allowing for improved breakdown and threshold voltages while maintaining a compact device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard isolation processes are used in miniaturized semiconductor structures, then manufacturing is simpler, but breakdown voltage becomes too low
Solution Approach 1:
The patent implements different isolation depths in different regions of the semiconductor device. High-voltage regions receive deeper isolations to achieve sufficient breakdown voltage, while low-voltage regions use shallower isolations. This local differentiation resolves the contradiction by providing enhanced reliability only where needed, rather than uniformly across the entire device, thus avoiding excessive manufacturing complexity in low-voltage areas.
Solution Approach 2:
The isolation structure is segmented into multiple depth levels corresponding to different voltage regions. The method divides the semiconductor substrate into high-voltage and low-voltage regions, and applies differentiated isolation processes to each segment. This segmentation allows the manufacturing process to achieve high breakdown voltage in critical areas without complicating the entire manufacturing flow.
2Reliability
If isolation depth is increased to meet high breakdown voltage requirements, then reliability improves, but device size becomes too large
Solution Approach 1:
The patent applies deeper isolations only in high-voltage regions where breakdown voltage requirements demand it, while using shallower isolations in low-voltage regions. This localized approach ensures that the increased device volume from deeper isolations is confined to only the necessary areas, maintaining compact overall device size while achieving the required reliability in high-voltage sections.
Solution Approach 2:
The patent differentiates isolation depth in the vertical dimension rather than expanding device footprint horizontally. By varying isolation depth (z-dimension) based on voltage region requirements, the solution achieves higher breakdown voltage without proportionally increasing the device's planar area, thus maintaining high packing density.
3Reliability
If deeper isolations are formed in high-voltage regions, then breakdown voltage increases, but manufacturing process becomes more complex
Solution Approach 1:
The manufacturing process is segmented into distinct steps for high-voltage and low-voltage regions. The patent uses separate photolithography and etching processes tailored to each voltage region's requirements. This segmentation allows each process step to be optimized independently, making the overall complex process more manageable and controllable compared to attempting a uniform deep isolation across the entire device.
Solution Approach 2:
The patent applies different manufacturing parameters (isolation depth, etching conditions) to different regions based on their voltage requirements. This localized manufacturing approach ensures that high-voltage regions receive the enhanced processing needed for deep isolations, while low-voltage regions undergo simpler processing, thereby balancing manufacturing complexity with reliability requirements.
4Productivity
If device size is reduced for high packing density, then productivity improves, but achieving high breakdown voltage becomes more difficult
Solution Approach 1:
The patent achieves high breakdown voltage in miniaturized devices by exploiting the vertical dimension through differentiated isolation depths. Instead of increasing device footprint to accommodate deeper isolations, the solution varies isolation depth (z-dimension) locally, allowing high-voltage regions to achieve sufficient breakdown voltage while maintaining compact planar dimensions for high packing density.
Solution Approach 2:
The patent provides enhanced isolation depth only in high-voltage regions of the miniaturized device, while using shallower isolations in low-voltage regions. This localized quality differentiation allows the device to maintain small overall size for high packing density while achieving the necessary breakdown voltage in critical high-voltage sections through targeted deep isolations.
Data Source
AI summary
A semiconductor structure includes a substrate including a first region and a second region; a first device disposed in the first region and a second device disposed in the second region; a first isolation disposed in the first region, wherein the first isolation is between a first source and a first drain, a first spacer overlaps the first isolation, the first isolation is separated from the first spacer by a first gate dielectric.