Self-Aligned Fin FET Gate Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
Existing fin transistor fabrication processes face challenges in precisely controlling the portion or layer of a semiconductor fin structure coupled to a gate electrode, leading to variable and undesirable transistor performance, particularly when using non-silicon materials like Ge, SiGe, and III-V compound semiconductors.
Innovation Solution
A method is developed where a gate electrode is self-aligned to a semiconductor fin, ensuring it strongly couples only to the channel residing on the fin side of a junctioned-semiconductor body without strongly coupling to the sub-fin side, thereby reducing parasitic gate capacitance and off-state leakage current. This is achieved by epitaxially growing a fin on a planarized sub-fin with a dielectric field isolation, where the gate stack lands on the top surface of the isolation, avoiding contact with the sub-fin sidewall.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fin fabrication processes are used, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to difficulty in precisely controlling the portion or layer of semiconductor fin structure coupled to gate electrode
Solution Approach 1:
The method performs preliminary actions by forming the gate electrode and gate dielectric before completing the fin structure. The gate stack is formed on a sacrificial layer, and the fin is subsequently grown epitaxially around the gate stack. This preliminary formation of the gate structure enables precise control of which fin portion couples to the gate electrode, as the fin growth automatically self-aligns to the gate edges, eliminating alignment issues that would occur with conventional post-gate fin formation methods
Solution Approach 2:
The fin structure performs self-alignment to the gate electrode through the epitaxial growth process. As the fin material grows epitaxially from the substrate, it automatically conforms to the gate stack geometry, with the fin sidewalls naturally aligning to the gate dielectric edges. This self-service mechanism eliminates the need for separate alignment steps and ensures precise control of the fin-gate coupling region without adding fabrication complexity
2Reliability
If the gate electrode couples to the sub-fin side, then gate control is extended, but parasitic gate capacitance increases leading to increased gate delay
Solution Approach 1:
The method extracts or removes the harmful coupling between the gate electrode and the sub-fin portion by using a sacrificial layer that prevents fin growth on the sub-fin side. The gate electrode is formed only over the channel-forming fin portion, and the epitaxial growth is blocked by the sacrificial layer, thereby eliminating parasitic gate capacitance from sub-fin coupling while maintaining necessary gate control over the channel region
Solution Approach 2:
A sacrificial layer acts as an intermediary element between the gate electrode and the sub-fin portion. This sacrificial material is deposited conformally, fills recesses, and prevents direct coupling between the gate and sub-fin during epitaxial growth. The sacrificial layer mediates the growth process to ensure the fin forms only where desired, eliminating parasitic capacitance while the gate maintains proper control over the channel-forming fin portion
3Strength
If the gate electrode couples to the sub-fin sidewall, then structural support is provided, but off-state leakage current increases
Solution Approach 1:
The method extracts or removes the harmful coupling between the gate electrode and the sub-fin sidewall by using a sacrificial layer that blocks fin growth in that region. The gate electrode is formed only over the channel-forming fin portion, and the epitaxial growth is blocked by the sacrificial layer, thereby eliminating parasitic gate capacitance from sub-fin coupling while maintaining necessary gate control over the channel region
Solution Approach 2:
A sacrificial layer acts as an intermediary element between the gate electrode and the sub-fin portion. This sacrificial material is deposited conformally, fills recesses, and prevents direct coupling between the gate and sub-fin during epitaxial growth. The sacrificial layer mediates the growth process to ensure the fin forms only where desired, eliminating parasitic capacitance while the gate maintains proper control over the channel-forming fin portion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The self-aligned gate electrode configuration enhances transistor performance by reducing gate delay and off-state leakage current, improving the reliability and consistency of transistors using high-mobility channel materials like Ge and III-V compounds.
Implementation Method 1
a dielectric field isolation planarized with an interface of the sub-fin and the fin
Implementation Method 2
epitaxially growing a fin on a planarized sub-fin
Data Source
AI summary
Monolithic FETs including a fin of a first semiconductor composition disposed on a sub-fin of a second composition. In some examples, an InGaAs fin is grown over GaAs sub-fin. The sub-fin may be epitaxially grown from a seeding surface disposed within a trench defined in an isolation dielectric. The sub-fin may be planarized with the isolation dielectric. The fin may then be epitaxially grown from the planarized surface of the sub-fin. A gate stack may be disposed over the fin with the gate stack contacting the planarized surface of the isolation dielectric so as to be self-aligned with the interface between the fin and sub-fin. Other embodiments may be described and/or claimed.