Multi-Path ESD Diode-SCR Layout for Low-Overshoot I/O Protection

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Solution Overview

Problem

Existing semiconductor devices face challenges with voltage overshoot during electrostatic discharge (ESD) events, particularly with diode string triggered SCRs (DTSCRs) and low voltage triggered SCRs (LVTSCRs, due to capacitance factors, which can damage integrated circuit devices.

Innovation Solution

The semiconductor device incorporates a configuration with diodes Dp, Dn, and Dn′, along with a power clamp circuit and resistance R, forming multiple ESD paths and equivalent silicon controlled rectifier (SCR) circuits to effectively discharge ESD current and reduce voltage drop across internal circuits, enhancing ESD robustness and reducing parasitic capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If DTSCR is used for ESD protection, then ESD protection capability is improved, but voltage overshoot occurs during ESD events

Engineering Contradiction:

ImproveESD protection capabilityVSAvoidvoltage overshoot

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent divides the ESD protection function into multiple independent paths: a first ESD path through a first SCR circuit and a second ESD path through a second SCR circuit. Each SCR circuit has its own trigger diode and discharge path, allowing the ESD current to be segmented and discharged through multiple parallel channels, thereby reducing voltage overshoot while maintaining protection capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces trigger diodes as intermediary elements that control the activation of each SCR circuit. The trigger diodes (D1, D2) act as mediators that sense the ESD event and selectively activate the appropriate SCR circuits, enabling controlled discharge of ESD current and preventing uncontrolled voltage overshoot.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Speed

If LVTSCR is used for ESD protection, then triggering speed is improved, but parasitic capacitance increases affecting high-speed applications

Engineering Contradiction:

Improvetriggering speedVSAvoidparasitic capacitance

Core Design Contradiction:

SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent employs different SCR circuit configurations with distinct parasitic capacitance characteristics in different locations of the circuit. The first SCR circuit and second SCR circuit are designed with different structural properties, allowing the system to utilize the local quality of each circuit to optimize both triggering speed and capacitance performance for specific application requirements.

Inventive Principle:

Principle #3Local quality

3Reliability

If multiple ESD paths are implemented, then ESD robustness is improved, but device complexity increases

Engineering Contradiction:

ImproveESD robustnessVSAvoidcircuit configuration

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple SCR circuits and their associated trigger diodes into a unified ESD protection structure. The first SCR circuit and second SCR circuit are combined in parallel, sharing common connection points and working together to provide enhanced ESD protection, thereby achieving robustness while managing complexity through systematic integration.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively discharges ESD current, reduces voltage drop, and improves ESD robustness for integrated circuit devices, enabling better protection against electrostatic discharge events while minimizing parasitic capacitance for high-speed applications.

Implementation Method 1

An ESD event produces extremely high voltages and leads to pulses of high current of a short duration that can damage integrated circuit devices

Methodology Applied

Scientific EffectElectrostatic Discharge: Electrostatic Discharge

Data Source

PatentUS20240178216A1Semiconductor device having multiple electrostatic discharge (ESD) paths

Publication Date: 2024.05.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.