3D-Stacked Nanosheet Transistors With Split Channel and Gate Dimensions
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Solution Overview
Problem
The performance of multi-stack semiconductor devices is limited when lower- and upper-stack nanosheet transistors have the same dimensions in their channel and gate structures, leading to suboptimal device performance and density.
Innovation Solution
The implementation of multi-stack semiconductor devices with different dimensions between the lower and upper channel and gate structures, including varying thicknesses of channel layers and gate structures, to enhance device performance and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lower- and upper-stack nanosheet transistors have the same dimensions in channel and gate structures, then manufacturing process is simplified, but device performance is limited
Solution Approach 1:
The patent applies local quality by giving different thickness dimensions to channel layers and gate structures at different vertical positions (lower stack vs upper stack). Specifically, the lower-stack nanosheet transistor has a first thickness for its channel layers and a first thickness for its gate structure, while the upper-stack nanosheet transistor has a second thickness for its channel layers and a second thickness for its gate structure, where these dimensions differ from the lower stack. This allows each region to be optimized for its specific performance requirements while maintaining a unified manufacturing process.
Solution Approach 2:
The patent implements parameter changes by varying the thickness parameters of channel layers and gate structures between lower and upper stacks. The channel layer thickness and gate structure thickness are changed as discrete parameters to optimize device performance. This enables independent optimization of electrical characteristics (such as mobility of holes and electrons) for different transistor stacks without requiring completely different manufacturing processes.
2Quantity of substance
If channel layers and gate structures have uniform thickness across stacks, then manufacturing precision is easier to maintain, but device density is reduced
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor device into distinct lower-stack and upper-stack nanosheet transistors with different dimensional characteristics. This segmentation allows each stack to have independently optimized thickness parameters for channel layers and gate structures, enabling higher device density through vertical integration of differently-sized transistors while maintaining manufacturing precision through a unified process that naturally produces the required dimensional variations.
Solution Approach 2:
The patent utilizes the vertical dimension (thickness direction) to differentiate between lower and upper stacks. By varying the thickness of channel layers and gate structures in the vertical dimension between stacks, the patent achieves higher device density without compromising manufacturing precision. The dimensional variation is implemented along the thickness direction rather than requiring complex lateral patterning differences.
3Reliability
If different thicknesses are used for lower and upper channel layers, then mobility optimization is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies universality by using a single unified manufacturing process that simultaneously produces both lower-stack and upper-stack nanosheet transistors with different thickness dimensions. The process is multi-functional, capable of creating dimensional variations between stacks without requiring separate fabrication sequences. This unified approach optimizes mobility for different transistor types while avoiding the complexity of multiple specialized manufacturing processes.
Data Source
AI summary
Provided is a multi-stack semiconductor device including: a substrate; a lower-stack nanosheet transistor including two or more lower channel layers surrounded by a lower gate structure, the lower channel layers connecting lower source/drain regions; and an upper-stack nanosheet transistor formed above the lower-stack nanosheet transistor, and including two or more upper channel layers surrounded by an upper gate structure, the upper channel layers connecting upper source/drain regions, wherein the lower-stack nanosheet transistor and the upper-stack nanosheet transistor have at least one of: a difference between a thickness of one of the lower channel layers and a thickness of one of the upper channel layers; and a difference between a thickness of the lower gate structure between two adjacent lower channel layers and a thickness of the upper gate structure between two adjacent upper channel layers.