Equal Thickness Metal Gate for VTFET CMOS Devices
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Solution Overview
Problem
Existing semiconductor devices with high-k metal gate (HKMG) technology face challenges in achieving equal gate thickness for n-type and p-type field effect transistors (FETs), which is critical for vertical transport field-effect transistors (VTFETs) in complementary metal oxide semiconductor (CMOS) devices.
Innovation Solution
A method involving the formation of first and second work function metals on nFET and pFET, with a sacrificial layer, to ensure the thickness of the metal gates of nFET and pFET are substantially the same, including the deposition of high-k dielectric layers and specific metal gate materials like TiN and TaN, and the use of masking and etching processes to achieve equal gate thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different work function metals are deposited on nFET and pFET to achieve proper threshold voltages, then the electrical characteristics of individual transistors are improved, but the gate thickness becomes unequal between nFET and pFET
Solution Approach 1:
The gate structure is segmented into multiple functional layers: a first work function metal layer for threshold voltage control, a second work function metal layer for thickness equalization, and a capping layer. This segmentation allows each layer to perform its specific function independently, resolving the contradiction between achieving proper threshold voltages and maintaining equal gate thickness.
Solution Approach 2:
The first work function metal layer is deposited on both nFET and pFET with different thicknesses to establish the required threshold voltages. Then, a second work function metal layer is deposited to compensate for the thickness difference and equalize the total gate thickness. This preliminary action on one transistor type followed by compensation on the other resolves the thickness uniformity issue.
2Manufacturing precision
If the metal gate thickness of nFET and pFET are made equal to improve device performance and reliability, then transistor capacitance increases and power consumption decreases, but the threshold voltage control becomes more difficult
Solution Approach 1:
Different local compositions are created within the gate structure by depositing different work function metals with different thicknesses on nFET and pFET. The first work function metal layer has different thicknesses on nFET and pFET to provide appropriate threshold voltages, while the second work function metal layer compensates to equalize total thickness. This local quality variation allows simultaneous achievement of threshold voltage control and thickness uniformity.
Solution Approach 2:
The gate structure uses composite materials consisting of multiple work function metal layers (e.g., TiN and TaN) with different electrical properties. This composite structure enables independent optimization of threshold voltage (through first layer composition) and gate thickness (through second layer compensation), resolving the contradiction between these two requirements.
3Manufacturing precision
If a multi-layer work function metal structure is used to achieve equal gate thickness, then the manufacturing process complexity increases, but the device performance is improved
Solution Approach 1:
The formation of equal-thickness metal gates on nFET and pFET is merged into a single sequential deposition process. The first work function metal layer is deposited on both transistor types, then the second work function metal layer is deposited to compensate for thickness differences. This merging of operations into one continuous process achieves thickness uniformity without requiring separate processing steps for each transistor type, thereby limiting the increase in manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the fabrication of semiconductor devices with nFET and pFET metal gates of equal thickness, enhancing the performance and reliability of VTFETs in CMOS devices by maintaining gate thickness within a ±10% margin, thus improving transistor capacitance and reducing power consumption.
Implementation Method 1
forming a high-k dielectric layer on a fin of an n-type field effect transistor (nFET) and on a fin of a p-type field effect transistor (pFET)
Implementation Method 2
forming a first work function metal and sacrificial layer on the high-k dielectric layer on the fin of the nFET and the fin of the pFET
Implementation Method 3
masking one of the nFET and the pFET
Implementation Method 4
removing the sacrificial layer and the first work function metal from the other of the nFET and the pFET
Data Source
AI summary
A semiconductor device includes an n-type field effect transistor (nFET) including a first fin and a first metal gate formed on the first fin, and a p-type field effect transistor (pFET) including a second fin and a second metal gate formed on the second fin, a thickness of the second metal gate being substantially the same as a thickness of the first metal gate.