FET Inrush Current Limiter Gate Control Across Wide Input Voltages
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Solution Overview
Problem
Existing inrush current limiting circuits using FETs face challenges in safely controlling the main switch across a wide supply voltage range due to the low voltage range requirements of FETs, making it difficult to effectively limit inrush currents in battery systems.
Innovation Solution
An inrush current limiter system that includes a field effect transistor, a gate driver with a voltage divider circuit and capacitor to adjust the turn-on time, and a high voltage limiter with a variable resistor to control the voltage rise, along with a low voltage releaser and feedback controller to manage voltage drops across a wide input voltage range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a FET with low on-resistance is used as the main switch to maintain low voltage drop, then the voltage drop after blocking inrush current is reduced, but the gate-source voltage must be maintained at 10V or more and the voltage between gate-source terminals must not exceed 20V, making it difficult to safely control the FET in battery systems with wide supply voltage range
Solution Approach 1:
A gate driver circuit is introduced as an intermediary between the power source and the FET gate terminal. This gate driver includes a voltage divider circuit that steps down the wide supply voltage to the appropriate gate-source voltage range (10-20V), and a voltage clamp circuit that prevents the gate-source voltage from exceeding the maximum 20V limit. This mediator enables safe FET control across wide input voltage ranges while maintaining low on-resistance for minimal voltage drop.
Solution Approach 2:
The gate driver circuit dynamically adjusts the gate-source voltage parameter based on the input voltage level. When input voltage exceeds the FET's maximum rating, the voltage clamp circuit activates to maintain gate-source voltage at or below 20V. The voltage divider circuit ensures the gate receives sufficient voltage (10V or more) to maintain low on-resistance. This parameter adjustment enables the FET to operate safely across wide supply voltage ranges.
2Loss of energy
If the FET is designed to operate with gate-source voltage of 10V or more for low on-resistance, then the voltage drop is minimized, but the voltage range for safe control is limited to maximum 20V, reducing adaptability to wide supply voltage ranges
Solution Approach 1:
The gate driver circuit serves as a voltage adaptation intermediary, accepting wide supply voltage inputs and transforming them into the precise 10-20V range required by the FET. The voltage divider circuit proportionally reduces high input voltages, while the voltage clamp circuit ensures the gate voltage never exceeds 20V. This intermediary enables the FET to maintain optimal performance across diverse battery system voltages without requiring circuit changes.
Solution Approach 2:
The gate driver circuit is designed to universally handle various input voltage levels by combining voltage division and clamping functions. This multi-functional circuitry allows the same FET design to be applied across different battery systems with varying voltage specifications, enhancing the overall adaptability and versatility of the inrush current limiting solution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system effectively limits inrush currents across a wide input voltage range, ensuring safe operation and minimizing voltage drops, thereby stabilizing the inrush current limiter and allowing it to be applied to battery systems without requiring circuit changes based on power source specifications.
Implementation Method 1
a first capacitor connected between the first input node and the control terminal of the field effect transistor, and configured to adjust a time until the field effect transistor may be turned-on after the input voltage may be input
Implementation Method 2
a high voltage limiter including a third resistor connected in parallel with the first resistor and having a resistance value varied according to a voltage between the first input node and the control terminal of the field effect transistor, and configured to limit a voltage rise between the first input node and the control terminal of the field effect transistor by varying resistance value of the third resistor
Data Source
Figure 1
Figure 2
Figure 3A
AI summary
An inrush current limiter includes first and second input nodes receiving an input voltage from a power source, first and second output nodes connected to a load, a field effect transistor connected between the first input node and the first output node, a gate driver including a first voltage divider circuit composed of a first resistor connected between the first input node and a control terminal of the field effect transistor and a second resistor connected between the control terminal of the field effect transistor and the second input node, and a first capacitor connected between the first input node and the control terminal of the field effect transistor, and configured to adjust a time until the field effect transistor may be turned-on after the input voltage may be input, and a high voltage limiter including a third resistor connected in parallel with the first resistor and having a resistance value varied according to a voltage between the first input node and the control terminal of the field effect transistor, and configured to limit a voltage rise between the first input node and the control terminal of the field effect transistor by varying resistance value of the third resistor.