1T-1R RRAM Cell Source Degeneration Inversion for Transistor Strength

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Solution Overview

Problem

Current 1T-1R RRAM cells experience source degeneration during the RESET operation, leading to weakened transistors and reduced voltage/current application, which affects the reliability and efficiency of memory devices as they scale down.

Innovation Solution

Allowing source degeneration to occur during the RRAM 'set' operation instead of 'reset', ensuring the transistor maintains full strength in both polarities, enabling higher voltage/current application and improving bit flip percentage and array yield without increasing cell size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If source degeneration is prevented during RESET operation, then transistor strength is maintained, but voltage/current application to RRAM is reduced

Engineering Contradiction:

Improvetransistor strengthVSAvoidvoltage/current application

Core Design Contradiction:

StrengthVSPower

Solution Approach 1:

The patent inverts the conventional approach by allowing source degeneration during SET operation instead of preventing it. This reversal enables the transistor to maintain full strength during RESET operation, ensuring maximum voltage and current application to the RRAM device when needed most for reliable reset functionality.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent changes the operational parameters by selectively enabling source degeneration during SET operation while maintaining full transistor strength during RESET operation. This parameter change optimizes the balance between transistor strength and voltage/current application across different operational phases.

Inventive Principle:

Principle #35Parameter changes

2Area of moving object

If transistor size is reduced for scaling, then device density increases, but voltage/current driving capability decreases

Engineering Contradiction:

Improvedevice densityVSAvoidvoltage/current driving capability

Core Design Contradiction:

Area of moving objectVSPower

Solution Approach 1:

The patent introduces dynamic control of source degeneration that adapts to the operational requirements. During SET operation, source degeneration is allowed to improve bit flip percentage, while during RESET operation, the transistor maintains full strength to ensure adequate voltage and current driving capability despite reduced device size.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

Inventive Principle:

Principle #35Parameter changes

3Quantity of substance

If RRAM dot size is increased, then memory capacity improves, but cell area increases

Engineering Contradiction:

Improvememory capacityVSAvoidcell area

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent changes the operational parameters to optimize the balance between transistor strength and voltage/current application. This enables larger RRAM dots to be integrated into the same cell area by improving the bit flip percentage through controlled source degeneration during SET operation.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the reliability and efficiency of RRAM devices by ensuring maximum voltage/current application, leading to better yield and allowing larger RRAM dots within the same cell size, thereby addressing the scaling challenges in semiconductor memory technology.

Implementation Method 1

Non-volatile memory devices such as an RRAM device depend on a phenomenon of resistance switching to store information. The non-volatile memory device functions as a variable resistor where the resistance of the device may switch between a high resistance state and a low resistance state.

Methodology Applied

Scientific EffectResistance switching: Electrical Resistance

Data Source

PatentUS11393526B2Thin film based 1T-1R cell with resistive random access memory below a bitline

Publication Date: 2022.07.19 INTEL CORP

AI summary

Described is a memory cell which comprises: a transistor positioned in a backend of a die, the transistor comprising: a source structure and a drain structure; a gate structure between the source structure and the drain structure; a source contact coupled to and above the source structure and a drain contact coupled to and below the drain structure; and a Resistive Random Access Memory (RRAM) device coupled to the drain contact.