Vertical Memory Devices Indium Gallium Channel Doping
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Solution Overview
Problem
Vertical memory devices face challenges in achieving uniform doping of impurities, leading to variations in threshold voltages and pad currents, which affect integration density and performance.
Innovation Solution
The implementation of polysilicon channels and pads doped with indium, gallium, carbon, and phosphorous, using low diffusion characteristics to maintain uniform doping profiles, and employing rapid thermal annealing to prevent diffusion during heat treatments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional doping methods are used in vertical memory devices, then manufacturing process is simple, but doping uniformity is poor leading to threshold voltage variations
Solution Approach 1:
The patent applies local quality by using different doping materials (indium and gallium) for different regions of the channel. Specifically, indium is used in the lower channel region while gallium is used in the upper channel region adjacent to the SSL. This regional differentiation addresses the doping uniformity issue by optimizing the electrical characteristics for each specific location within the vertical channel structure, thereby reducing threshold voltage variations without requiring complex multi-step doping processes.
Solution Approach 2:
The patent employs parameter changes by carefully controlling the doping concentration gradients of indium and gallium throughout the channel structure. By adjusting the concentration parameters of different dopants in different vertical regions, the invention achieves uniform doping characteristics and consistent threshold voltages across memory cells, while maintaining a relatively simple single-step or sequential doping manufacturing process.
2Manufacturing precision
If indium and gallium doping is implemented in the channel, then threshold voltage uniformity is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies local quality by using different doping materials (indium and gallium) for different regions of the channel. Specifically, indium is used in the lower channel region while gallium is used in the upper channel region adjacent to the SSL. This regional differentiation addresses the doping uniformity issue by optimizing the electrical characteristics for each specific location within the vertical channel structure, thereby reducing threshold voltage variations without requiring complex multi-step doping processes.
Solution Approach 2:
The patent employs parameter changes by carefully controlling the doping concentration gradients of indium and gallium throughout the channel structure. By adjusting the concentration parameters of different dopants in different vertical regions, the invention achieves uniform doping characteristics and consistent threshold voltages across memory cells, while maintaining a relatively simple single-step or sequential doping manufacturing process.
3Stability of the object's composition
If carbon doping is added to the channel, then diffusion during heat treatment is reduced, but manufacturing steps increase
Solution Approach 1:
The patent applies merging by combining carbon doping with the indium and gallium doping in a single integrated doping step or closely coupled sequential steps. The carbon dopant is introduced together with or immediately following the indium-gallium doping sequence, allowing the doping profile to be established and stabilized simultaneously. This combination approach prevents diffusion during subsequent heat treatments while avoiding the need for separate, complex manufacturing steps, thus maintaining doping profile stability without significantly increasing process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced threshold voltage and source/drain resistance distributions, enhancing the integration density and performance of vertical memory devices.
Implementation Method 1
the channel may include polysilicon doped with indium and/or gallium at a portion thereof adjacent to the SSL
Implementation Method 2
The channel may be further doped with carbon at the portion thereof adjacent to the SSL
Implementation Method 3
employing rapid thermal annealing to prevent diffusion during heat treatments
Implementation Method 4
Prior to doping the portion of the preliminary channel with indium and/or gallium, silicon ions and/or germanium ions may be implanted into the preliminary channel to amorphousize the preliminary channel
Data Source
AI summary
A vertical memory device may include a substrate, a first selection line on the substrate, a plurality of word lines on the first selection line, a second selection line on the plurality of word lines, and a semiconductor channel. The first selection line may be between the plurality of word lines and the substrate, and the plurality of word lines may be between the first and second selection lines. Moreover, the first and second selection lines and the plurality of word lines may be spaced apart in a direction perpendicular with respect to a surface of the substrate. The semiconductor channel may extend away from the surface of the substrate adjacent sidewalls of the first and second selection lines and the plurality of word lines. In addition, portions of the semiconductor channel adjacent the second selection line may be doped with indium and/or gallium. Related methods are also discussed.