BSPDN Power Gating Transistor Layout for Standby Leakage Control
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Solution Overview
Problem
Nanosheet technology in CMOS scaling faces issues with leakage in standby mode, and there is a lack of an economical process for controlling this leakage when using a backside-power-distribution-network.
Innovation Solution
The design incorporates header and footer gate transistors in parallel with logic devices, connected to VSS or VDD sources, which act as switches to disconnect power and ground during standby mode, reducing leakage by controlling the backside-power-distribution-network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If nanosheet technology is used for CMOS scaling, then device performance is improved, but leakage in standby mode increases
Solution Approach 1:
The power distribution network is segmented by introducing header and footer gate transistors that can independently control power (VDD) and ground (VSS) connections to the logic device. This segmentation allows selective disconnection of power supplies during standby mode, reducing leakage while maintaining performance during active mode.
Solution Approach 2:
Header and footer gate transistors are introduced as intermediary components between the power distribution network and the logic device. These gate transistors act as controllable switches that mediate the connection between power/ground and the logic device, enabling precise control over leakage current paths during standby mode.
2Loss of energy
If header and footer gate transistors are added to control leakage, then leakage reduction is achieved, but device complexity increases
Solution Approach 1:
The header and footer gate transistors are merged with the existing logic device structure, sharing common substrate and interconnect resources. This integration approach reduces the overall device complexity compared to adding completely separate power control circuits, while still achieving effective leakage control.
Solution Approach 2:
The gate transistors serve multiple functions: they act as switches for power control during standby mode, provide leakage protection, and can potentially be used for dynamic power management. This multi-functionality reduces the need for additional dedicated components, thereby limiting the increase in device complexity.
Data Source
AI summary
A microelectronic architecture including a logic device and a header gate transistor located adjacent to a first side of the logic device. The header gate transistor has a parallel orientation to the logic device, and the header gate transistor is connected to a VSS source or a VDD source. Aa footer gate transistor located adjacent to a second side of the logic device and the footer gate transistor has parallel orientation to the logic device. The first side and the second side are opposite sides of the logic device and the footer gate transistor is connected to a VSS source or a VDD source. The footer gate transistor is connected to a different source than the header gate transistor and the logic device is connected to the VSS source and the VDD source through either footer gate transistor and the header gate transistor.