Backside Contact Air Spacer Structure for Parasitic Capacitance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to scale down, challenges arise in maintaining device performance and reducing fabrication costs, particularly in forming effective backside contacts for field-effect transistors, where conventional methods are not entirely satisfactory in reducing parasitic capacitance and improving device complexity.
Innovation Solution
The implementation of an air spacer, formed by depositing a sacrificial material along the sidewalls of a trench and removing it to create a gap surrounding a metal contact, which reduces capacitance and enhances device performance by using a dielectric layer and conductive material to fill the trench, thereby improving the backside contact effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional backside contact methods are used, then fabrication process is simpler, but parasitic capacitance is higher and device performance is reduced
Solution Approach 1:
A dielectric layer is introduced as an intermediary between the metal contact and the surrounding environment. This dielectric layer acts as a mediator that reduces parasitic capacitance while maintaining the electrical connection, thus improving device performance without requiring fundamental changes to the backside contact structure
Solution Approach 2:
The patent modifies the electrical parameters of the backside contact by changing the dielectric properties of the surrounding material. By controlling the dielectric constant and thickness of the dielectric layer, the parasitic capacitance is reduced, thereby improving device performance while maintaining fabrication compatibility
2Productivity
If device size is scaled down, then production efficiency increases and costs decrease, but device performance degradation and fabrication complexity increase
Solution Approach 1:
By scaling the dielectric layer thickness and material properties alongside device miniaturization, the patent maintains optimal electrical characteristics. This allows continued scaling for improved productivity while preventing performance degradation through controlled parameter adjustments
Solution Approach 2:
The dielectric layer is formed as part of the backside contact structure before final device assembly. This preliminary action ensures that parasitic capacitance is minimized from the outset, preventing performance issues before they arise during device operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance, improving the performance of field-effect transistors by creating an air gap that enhances the effectiveness of the backside contact, allowing for better gate control and reduced short-channel effects, while maintaining aggressive scaling and compatibility with CMOS processes.
Implementation Method 1
The air spacer reduces parasitic capacitance, improving the performance of field-effect transistors
Data Source
AI summary
A method includes performing a first etching process on a backside of a substrate to expose a dummy contact structure, performing a first deposition process to deposit a first dielectric layer around the dummy contract structure, performing a second deposition process to deposit an oxide layer on the first dielectric layer, removing the dummy contract structure to form a trench, depositing a sacrificial layer on sidewalls of the trench, depositing a second dielectric layer on the sacrificial layer, filling the trench with a conductive material, and removing the sacrificial layer to form an air spacer between the first dielectric layer and the second dielectric layer.